鈩?/div>
@ 10V
OPTIMAL R
DS
(on) x Qg TRADE-OFF @ 4.5V
CONDUCTION LOSSES REDUCED
SWITCHING LOSSES REDUCED
DESCRIPTION
This application specific Power MOSFET is the
second generation of STMicroelectronis unique
"Single Feature Size鈩?quot; strip-based process. The
resulting transistor shows the best trade-off
between on-resistance and gate charge. Such
features make it the best choice in high efficiency
DC-DC converters for Telecom and computer
industries.
APPLICATIONS
s
DC-DC CONVERTERS FOR TELECOM AND
NOTEBOOK CPU CORE
s
SYNCHRONOUS RECTIFIER
SO-8
INTERNAL SCHEMATIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol
V
DS
V
DGR
V
GS
I
D
I
D
I
DM
(鈥?
P
tot
Parameter
Drain-source Voltage (V
GS
= 0)
Drain-gate Voltage (R
GS
= 20 k鈩?
Gate- source Voltage
Drain Current (continuous) at T
C
= 25擄C
Drain Current (continuous) at T
C
= 100擄C
Drain Current (pulsed)
Total Dissipation at T
C
= 25擄C
Value
30
30
鹵 18
17
12
68
3.2
Unit
V
V
V
A
A
A
W
(鈥?
Pulse width limited by safe operating area.
March 2003
.
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