鈩⑩€?/div>
strip-based process. The resulting tran-
sistor shows extremely high packing density for
low on-resistance, rugged avalance characteris-
tics and less critical alignment steps therefore a re-
markable manufacturing reproducibility.
D
2
PAK
INTERNAL SCHEMATIC DIAGRAM
APPLICATIONS
s
SOLENOID AND RELAY DRIVERS
s
MOTOR CONTROL, AUDIO AMPLIFIERS
s
DC-DC CONVERTERS
s
AUTOMOTIVE ENVIRONMENT
ABSOLUTE MAXIMUM RATINGS
Symbol
V
DS
V
DGR
V
GS
I
D
(1)
I
D
(1)
I
DM
( )
P
TOT
dv/dt (2)
E
AS
(3)
T
stg
T
j
Parameter
Drain-source Voltage (V
GS
= 0)
Drain-gate Voltage (R
GS
= 20 k鈩?
Gate- source Voltage
Drain Current (continuos) at T
C
= 25擄C
Drain Current (continuos) at T
C
= 100擄C
Drain Current (pulsed)
Total Dissipation at T
C
= 25擄C
Derating Factor
Peak Diode Recovery voltage slope
Single Pulse Avalanche Energy
Storage Temperature
Max. Operating Junction Temperature
Value
55
55
鹵 16
80
80
320
300
2
15
870
鈥?5 to 175
175
(1) Current Limited by Package
(2) I
SD
鈮?0A,
di/dt
鈮?00A/碌s,
V
DD
=40V T
j
鈮?/div>
T
JMAX.
(3) Starting T
j
=25擄C, I
D
=40A, V
DD
=40V
Unit
V
V
V
A
A
A
W
W/擄C
V/ns
mJ
擄C
擄C
(
q
) Pulse width limited by safe operating area
April 2003
1/8
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