鈩?/div>
EXTREMELY HIGH dv/dt AND CAPABILITY GATE
TO - SOURCE ZENER DIODES
100% AVALANCHE TESTED
VERY LOW GATE INPUT RESISTANCE
GATE CHARGE MINIMIZED
D虜PAK
1
2
3
TO-220
TO-220FP
12
3
DESCRIPTION
The third generation of MESH OVERLAY鈩?Power
MOSFETs for very high voltage exhibits unsurpassed
on-resistance per unit area while integrating back-to-
back Zener diodes between gate and source. Such ar-
rangement gives extra ESD capability with higher rug-
gedness performance as requested by a large variety
of single-switch applications.
APPLICATIONS
SINGLE-ENDED SMPS IN MONITORS,
COMPUTER AND INDUSTRIAL APPLICATION
s
WELDING EQUIPMENT
s
I虜PAK
(Tabless TO-220)
INTERNAL SCHEMATIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol
V
DS
V
DGR
V
GS
I
D
I
D
I
DM
(1)
P
TOT
I
GS
V
ESD(G-S)
dv/dt
V
ISO
T
stg
T
j
Parameter
Drain-source Voltage (V
GS
= 0)
Drain-gate Voltage (R
GS
= 20 k鈩?
Gate- source Voltage
Drain Current (continuous) at T
C
= 25擄C
Drain Current (continuous) at T
C
= 100擄C
Drain Current (pulsed)
Total Dissipation at T
C
= 25擄C
Derating Factor
Gate-source Current
Gate source ESD(HBM-C=100pF, R=15K鈩?
Peak Diode Recovery voltage slope
Insulation Winthstand Voltage (DC)
Storage Temperature
Max. Operating Junction Temperature
--
鈥?5 to 150
150
4.6
2.9
18.4
100
0.8
鹵 50
3
3
2000
Value
STP(B)5NC70Z(-1)
700
700
鹵 25
4.6(*)
2.9(*)
18.4
35
0.32
STP5NC70ZFP
V
V
V
A
A
A
W
W/擄C
mA
KV
V/ns
V
擄C
擄C
Unit
(1)Pulse width limited by safe operating area
December 2002
(
q
)I
SD
鈮?.5A,
di/dt
鈮?00A/碌s,
V
DD
鈮?/div>
V
(BR)DSS
, T
j
鈮?/div>
T
JMAX
(*)
.
Limited only by maximum temperature allowed
1/12
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