鈩?/div>
EXCEPTIONAL dv/dt CAPABILITY
100% AVALANCHE TESTED
LOW GATE CHARGE AT 100
o
C
APPLICATION ORIENTED
CHARACTERIZATION
3
1
2
DESCRIPTION
This Power MOSFET is the latest development of
STMicroelectronics unique 鈥漇ingle Feature
Size鈩⑩€?strip-based
process. The resulting
transistor shows extremely high packing density
for low on-resistance, rugged avalanche
characteristics and less critical alignment steps
therefore
a
remarkable
manufacturing
reproducibility.
APPLICATIONS
s
HIGH CURRENT, HIGH SPEED SWITCHING
s
SOLENOID AND RELAY DRIVERS
s
MOTOR CONTROL, AUDIO AMPLIFIERS
s
DC-DC & DC-AC CONVERTERS
s
AUTOMOTIVE ENVIRONMENT
TO-220
INTERNAL SCHEMATIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol
V
DS
V
DGR
V
GS
I
D
I
D
I
DM
(鈥?
P
tot
Parameter
Drain-source Voltage (V
GS
= 0)
Drain- gate Voltage (R
GS
= 20 k鈩?
G ate-source Voltage
Drain Current (continuous) at T
c
= 25
o
C
Drain Current (continuous) at T
c
= 100
o
C
Drain Current (pulsed)
T otal Dissipation at T
c
= 25 C
Derating Factor
dv/dt (
1
) Peak Diode Recovery voltage slope
T
s tg
T
j
Storage Temperature
Max. Operating Junction Temperature
o
Value
100
100
鹵
20
50
35
200
150
1
6
-65 to 175
175
(
1
) I
SD
鈮?/div>
50 A, di/dt
鈮?/div>
300 A/碌s, V
DD
鈮?/div>
V
(BR)DSS
, T
j
鈮?/div>
T
JMAX
Un it
V
V
V
A
A
A
W
W /
o
C
V/ns
o
o
C
C
(鈥? Pulse width limited by safe operating area
April 1999
1/8
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