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STP4NB30

STP4NB30FP

N-CHANNEL 300V - 1.8鈩?- 4A - TO-220/TO-220FP

PowerMesh鈩?MOSFET

TYPE

STP4NB30

STP4NB30FP

s

V

DSS

300 V

R

DS(on)

<2

鈩?/div>

<2

鈩?/div>

I

D

4A

TYPICAL R

DS

(on) = 1.8

鈩?/div>

EXTREMELY HIGH dv/dt CAPABILITY

100% AVALANCHE TESTED

NEW HIGH VOLTAGE BENCHMARK

GATE CHARGE MINIMIZED

TO-220

3

1

2

3

1

2

DESCRIPTION

Using the latest high voltage MESH OVERLAY鈩?/div>

process, STMicroelectronics has designed an ad-

vanced family of power MOSFETs with outstanding

performances. The new patent pending strip layout

coupled with the Company鈥檚 proprieraty edge termi-

nation structure, gives the lowest RDS(on) per area,

exceptional avalanche and dv/dt capabilities and

unrivalled gate charge and switching characteris-

tics.

APPLICATIONS

s

HIGH CURRENT, HIGH SPEED SWITCHING

s

SWITH MODE POWER SUPPLIES (SMPS)

s

DC-AC CONVERTERS FOR TELECOM,

INDUSTRIAL AND CONSUMER

ENVIRONMENT

ABSOLUTE MAXIMUM RATINGS

Symbol

V

DS

V

DGR

V

GS

I

D

I

D

I

DM

(1)

P

TOT

dv/dt

V

ISO

T

stg

T

j

Parameter

Drain-source Voltage (V

GS

= 0)

Drain-gate Voltage (R

GS

= 20 k鈩?

Gate- source Voltage

Drain Current (continuos) at T

C

= 25擄C

Drain Current (continuos) at T

C

= 100擄C

Drain Current (pulsed)

Total Dissipation at T

C

= 25擄C

Derating Factor

Peak Diode Recovery voltage slope

Insulation Withstand Voltage (DC)

Storage Temperature

Max. Operating Junction Temperature

TO-220FP

INTERNAL SCHEMATIC DIAGRAM

Value

STP4NB30

300

鹵30

4

2.5

16

70

0.56

4

-

鈥?5 to 150

150

(1)I

SD

鈮?

A, di/dt

鈮?00A/碌s,

V

DD

鈮?/div>

V

(BR)DSS

, T

j

鈮?/div>

T

JMAX

(*) Limited only by Maximum Temperature Allowed

Unit

V

4 (*)

2.5 (*)

16 (*)

30

0.24

2000

A

W

W/擄C

V/ns

V

擄C

STP4NB30FP

(鈥?Pulse width limited by safe operating area

May 2001

1/9

型號(hào)

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STP4NB30FP Datasheet

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