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STP4NA100 Datasheet

  • STP4NA100

  • N - CHANNEL ENHANCEMENT MODE FAST POWER MOS TRANSISTOR

  • 5頁

  • STMICROELECTRONICS   STMICROELECTRONICS

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STP4NA100
N - CHANNEL ENHANCEMENT MODE
FAST POWER MOS TRANSISTOR
PRELIMINARY DATA
TYPE
STP4NA100
s
s
s
s
s
s
s
V
DSS
1000 V
R
DS(on)
<3. 5
鈩?/div>
I
D
4.2 A
TYPICAL R
DS(on)
= 2.9
鈩?/div>
鹵
30V GATE TO SOURCE VOLTAGE RATING
100% AVALANCHE TESTED
REPETITIVE AVALANCHE DATA AT 100
o
C
LOW INTRINSIC CAPACITANCES
GATE CHARGE MINIMIZED
REDUCED THRESHOLD VOLTAGE SPREAD
1
3
2
DESCRIPTION
This series of POWER MOSFETS represents
the most advanced high voltage technology.
The optmized cell layout coupled with a new
proprietary edge termination concur to give
the device low RDS(on) and gate charge,
unequalled
ruggedness
and
superior
switching performance.
APPLICATIONS
s
HIGH CURRENT, HIGH SPEED SWITCHING
s
SWITCH MODE POWER SUPPLIES (SMPS)
s
DC-AC CONVERTERS FOR WELDING
EQUIPMENT AND UNINTERRUPTIBLE
POWER SUPPLIES AND MOTOR DRIVE
TO-220
INTERNAL SCHEMATIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol
V
DS
V
DGR
V
GS
I
D
I
D
I
DM
(鈥?
P
tot
T
stg
T
j
Parameter
Drain-source Voltage (V
GS
= 0)
Drain- gate Voltage (R
GS
= 20 k鈩?
Gate-source Voltage
Drain Current (continuous) at T
c
= 25
o
C
Drain Current (continuous) at T
c
= 100
o
C
Drain Current (pulsed)
Total Dissipation at T
c
= 25
o
C
Derating Factor
Storage Temperature
Max. Operating Junction Temperature
Value
1000
1000
鹵
30
4.2
2.6
16.8
125
1
-65 to 150
150
Unit
V
V
V
A
A
A
W
W/
o
C
o
C
o
C
(鈥? Pulse width limited by safe operating area
October 1997
1/5

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