(on) = 3.2鈩?/div>
EXTREMELY HIGH dv/dt AND CAPABILITY GATE
TO - SOURCE ZENER DIODES
100% AVALANCHE TESTED
VERY LOW GATE INPUT RESISTANCE
GATE CHARGE MINIMIZED
TO-220
TO-220FP
12
3
DESCRIPTION
The third generation of MESH OVERLAY鈩?Power
MOSFETs for very high voltage exhibits unsurpassed
on-resistance per unit area while integrating back-to-
back Zener diodes between gate and source. Such ar-
rangement gives extra ESD capability with higher rug-
gedness performance as requested by a large variety
of single-switch applications.
APPLICATIONS
s
SINGLE-ENDED SMPS IN MONITORS,
COMPUTER AND INDUSTRIAL APPLICATION
s
WELDING EQUIPMENT
ABSOLUTE MAXIMUM RATINGS
Symbol
V
DS
V
DGR
V
GS
I
D
I
D
I
DM
(
q
)
P
TOT
I
GS
V
ESD(G-S)
dv/dt
V
ISO
T
stg
T
j
January 2001
Parameter
Drain-source Voltage (V
GS
= 0)
Drain-gate Voltage (R
GS
= 20 k鈩?
Gate- source Voltage
Drain Current (continuos) at T
C
= 25擄C
Drain Current (continuos) at T
C
= 100擄C
Drain Current (pulsed)
Total Dissipation at T
C
= 25擄C
Derating Factor
Gate-source Current (*)
Gate source ESD(HBM-C=100pF, R=15K鈩?
Peak Diode Recovery voltage slope
Insulation Withstand Voltage (DC)
Storage Temperature
Max. Operating Junction Temperature
--
I2PAK
(Tabless TO-220)
Value
STP(B)3NC90Z(-1)
900
900
鹵 25
3.5
2.2
14
100
0.8
鹵50
2.5
3
2000
鈥?5 to 150
150
(1)I
SD
鈮?.5A,
di/dt
鈮?00A/碌s,
V
DD
鈮?/div>
V
(BR)DSS
, T
j
鈮?/div>
T
JMAX
(*)
.
Limited only by maximum temperature allowed
Unit
STP3NC90ZFP
V
V
V
3.5(*)
2.2(*)
14
35
0.28
A
A
A
W
W/擄C
mA
KV
V/ns
V
擄C
擄C
1/11
(鈥?Pulse width limited by safe operating area
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