(on) = 4.1鈩?/div>
EXTREMELY HIGH dv/dt AND CAPABILITY
GATE TO - SOURCE ZENER DIODES
100% AVALANCHE TESTED
VERY LOW GATE INPUT RESISTANCE
GATE CHARGE MINIMIZED
TO-220
TO-220FP
3
1
2
DESCRIPTION
The third generation of MESH OVERLAY鈩?Power
MOSFETs for very high voltage exhibits unsur-
passed on-resistance per unit area while integrat-
ing back-to-back Zener diodes between gate and
source. Such arrangement gives extra ESD capa-
bility with higher ruggedness performance as re-
quested by a large variety of single-switch
applications.
APPLICATIONS
s
SINGLE-ENDED SMPS IN MONITORS,
COMPUTER AND INDUSTRIAL APPLICATION
s
WELDING EQUIPMENT
ABSOLUTE MAXIMUM RATINGS
Symbol
V
DS
V
DGR
V
GS
I
D
I
D
I
DM
(
q
)
P
TOT
I
GS
V
ESD(G-S)
dv/dt (1)
V
ISO
T
stg
T
j
June 2001
Parameter
Drain-source Voltage (V
GS
= 0)
Drain-gate Voltage (R
GS
= 20 k鈩?
Gate- source Voltage
Drain Current (continuos) at T
C
= 25擄C
Drain Current (continuos) at T
C
= 100擄C
Drain Current (pulsed)
Total Dissipation at T
C
= 25擄C
Derating Factor
Gate-source Current (DC)
Gate source ESD(HBM-C=100pF, R=1.5K鈩?
Peak Diode Recovery voltage slope
Insulation Withstand Voltage (DC)
Storage Temperature
Max. Operating Junction Temperature
-
鈥?5 to 150
150
(*) Limited by Maximum Temperature allowed
Value
STP3NC70Z
700
700
鹵 25
2.5
1.6
10
65
0.52
鹵50
1.5
3
2500
2.5 (*)
1.6 (*)
10
35
0.28
STP3NC70ZFP
Unit
V
V
V
A
A
A
W
W/擄C
mA
KV
V/ns
V
擄C
擄C
1/10
(鈥?Pulse width limited by safe operating area
(1) I
SD
鈮?.5A,
di/dt
鈮?00A/碌s,
V
DD