STMicroelectronics unique 鈥漇ingle Feature Size鈥?/div>
process whereby a single body is implanted on a
strip layout structure. The resulting transistor
shows extremely high packing density for low on-
resistance, rugged avalance characteristics and
less critical alignment steps therefore a remarka-
ble manufacturing reproducibility.
APPLICATIONS
s
DC MOTOR CONTROL
s
DC-DC & DC-AC CONVERTERS
s
SYNCHRONOUS RECTIFICATION
ABSOLUTE MAXIMUM RATINGS
Symbol
V
DS
V
DGR
V
GS
I
D
I
D
I
DM
(鈥?
P
tot
V
ISO
dV/dt
T
s tg
T
j
鈥?/div>
TO-220FP
INTERNAL SCHEMATIC DIAGRAM
Parameter
Drain-source Voltage (V
GS
= 0)
Drain- gate Voltage (R
GS
= 20 k
鈩?/div>
)
G ate-source Voltage
Drain Current (continuous) at T
c
= 25
o
C
Drain Current (continuous) at T
c
= 100
o
C
Drain Current (pulsed)
T otal Dissipation at T
c
= 25 C
Derating Factor
Insulation W ithstand Voltage (DC)
Peak Diode Recovery voltage slope
Storage Temperature
Max. Operating Junction Temperature
o
Value
STP30NE06
STP30NE06FP
60
60
鹵
20
30
21
120
80
0.53
錚?/div>
7
-65 to 175
175
(
1
) I
SD
鈮?/div>
30 A, di/dt
鈮?/div>
300 A/
碌
s, V
DD
鈮?/div>
V
(BR)DSS
, T
j
鈮?/div>
T
JMAX
Un it
V
V
V
17
12
68
30
0.2
2000
A
A
A
W
W /
o
C
V
V/ns
o
o
C
C
(
鈥?/div>
) Pulse width limited by safe operating area
January 1999
1/6
STP30NE06 產(chǎn)品屬性
STMicroelectronics
N-Channel
60 V
+/- 20 V
30 A
0.042 Ohms
Single
+ 175 C
Through Hole
TO-220
Tube
41 ns
- 65 C
80 W
95 ns
50
STP30NE06相關(guān)型號(hào)PDF文件下載
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