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STP1081ABGA-150 Datasheet

  • STP1081ABGA-150

  • ASIC

  • 32頁

  • ETC

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STP1081
July 1997
UltraSPARC
鈩?/div>
-II Data Buffer (UDB-II)
DATA SHEET
D
ESCRIPTION
The UltraSPARC-II Data Buffer (UDB-II) consists of two identical ASICs connecting the UltraSPARC-II micro-
processor and its E-Cache to the system data bus (i.e., UPA bus). These two are designated UDB_H (for the
most-signi鏗乧ant data bits) and UDB_L (for the least-signi鏗乧ant data bits). The UDB-II moves data between the
E-Cache bus and the UPA data bus (see
Figure 1),
enabling the system to send data to and receive data from
the faster CPU transparently. The E-Cache bus has 128 data bits and 16 parity bits, for a total width of 144 bits.
The data bus is also 144 bits wide, including 128 data bits and 16 error-correction code (ECC) bits. Noncache-
able loads and stores use the E-Cache bus for moving data to the data buffer located in UDB_H and UDB_L.
The UDB-II (model STP1081ABGA) is built with leading-edge CMOS ASIC technology featuring 0.5-micron
geometries, and a three-layer metal process. It operates at 2.6 V and 3.3 V.
Companion Device for 250/300 MHz UltraSPARC-II Systems
Features
鈥?Isolates the processor from the system bus
鈥?Interface to the UPA
鈥?Operates at system frequency
鈥?Operates at half the processor frequency
鈥?Provides data buffering
鈥?Supports parity on the CPU side and ECC on the system
side
鈥?Stores interrupt vectors. Interrupt registers visible to
software
鈥?IEEE standard 1149.1 (JTAG) boundary scan test
鈥?256 PBGA package
Bene鏗乼s
鈥?High performance: ease of design
鈥?Fully synchronous design
鈥?Enables secondary cache transfers and system memory
transfers by isolation
鈥?Ease of manufacturing test
鈥?Small footprint and cost effective packaging
1
This Material Copyrighted by Its Respective Manufacturer

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