STLC1510
NorthenLite鈩?G.lite DMT Transceiver
PRODUCT PREVIEW
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ATM transport
Forward Error correction & interleaving
Framing & de-framing
DMT modulation and demodulation
Start-up & showtime control processing
LBGA132
ORDERING NUMBER: STLC1510
In addition, the STLC1510 provides the following fea-
tures:
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Serial and Parallel network interface at back-
end to CO equipment
Serial interface to the AFE chip STLC1511
Access to off chip memory
Power-up boot program stored in ROM
132 balls 12x12x1.7 mm LBGA package
Power Consumption: 0.75 Watt
Power Supp.: 2.5 V (core) and 3.3 V (I/O ring)
1.0 GENERAL DESCRIPTION
The STLC1510 is a high-speed modem chip that pro-
vides the digital portion of a G.992.2 DSL access at a
Central Office (CO) site. It provides downstream and
upstream data transport between an ATM byte
stream and an analog front-end chip using Discrete
Multi-Tone (DMT) Modulation.
The STLC1510 is compliant with ITU-T G.992.2
(G.Lite), G.996.1 (G.Test), G.994.1 (G.Handshake),
G.997.1 (G.Ploam).
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Figure 1. Block Diagram
EN_D 950_E M U
HP I_Data[7:0]
8
HP I_Addr[2:0]
3
ARM 2HP _IN T
AR M_M ODE
LinDr_A GC2
LinDr_AG C1
LinD r_Peak
H PI_RWN
HP I_CLK
HP I_CSN
HP I_ASN
TxClk
TxClav
TxEnb
TxSOC
U TxData [7 :0 ]
TxAddr[4:0 ]
TxParity
TxBP
RxClk
R xClav
RxSOC
URxData [ 7:0]
RxAddr[4: 0]
RxParity
RxEnb
HPI
DFE
EPM
me m
m em
m em
BPU
m em
m em
FEC
MAP
pgm
NIF
TxSOUT[1 :0 ]
A_SCLK
CK35M
RxSIN[1 : 0]
L AMB A Bus
7
7
REF_CLK
VDD3_3
VDD2_5
VSS
TAP
2
2
8
T GB
ctrl
AR M
D95 0
Dual
MAC
SPI_ CLK
SPI_ ENB
14
SPI_ DTX
SPI_ DRX
TD I
Pmode[1:0]
C Mode[1:0]
D 950_CMO DE
TCK
TM S
TRSTN
GP IO[7:0]
VDD_PLL
Guard_PLL
VS S_PLL
RES ETN
VCODC
TDO
INF_OUT
November 2000
This is preliminary information on a new product now in development. Details are subject to change without notice.
R E F_ O U T
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