(on) = 0.025鈩?/div>
IMPROVED DIE-TO-FOOTPRINT RATIO
VERY LOW PROFILE PACKAGE
DESCRIPTION
This Power MOSFET is the second generation of
STMicroelectronics unique 鈥淪TripFET鈩⑩€?technolo-
gy. The resulting transistor shows extremely low on-
resistance and minimal gate charge. The new Pow-
erFLAT鈩?package allows a significant reduction in
board space without compromising performance.
PowerFLAT鈩?6x5)
(Chip Scale Package)
INTERNAL SCHEMATIC DIAGRAM
APPLICATIONS
s
HIGH EFFICIENCY ISOLATED DC/DC
CONVETERS
ABSOLUTE MAXIMUM RATINGS
Symbol
V
DS
V
DGR
V
GS
I
D
I
DM
(
q
)
P
TOT
E
AS
(1)
T
stg
T
j
Parameter
Drain-source Voltage (V
GS
= 0)
Drain-gate Voltage (R
GS
= 20 k鈩?
Gate- source Voltage
Drain Current (continuos) at T
C
= 25擄C
Drain Current (continuos) at T
C
= 100擄C
Drain Current (pulsed)
Total Dissipation at T
C
= 25擄C
Derating Factor
Single Pulse Avalanche Energy
Storage Temperature
Max. Operating Junction Temperature
Value
100
100
鹵 20
35
22
140
80
0.64
135
鈥?5 to 150
鈥?5 to 150
Unit
V
V
V
A
A
A
W
W/擄C
mJ
擄C
擄C
(
q
) Pulse width limited by safe operating area
(1) Starting T
j
= 25擄C, I
D
= 35A, V
DD
= 50V
August 2001
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