(on) = 0.024鈩?/div>
IMPROVED DIE-TO-FOOTPRINT RATIO
VERY LOW PROFILE PACKAGE
DESCRIPTION
This Power MOSFET is the second generation of
STMicroelectronics unique 鈥淪TripFET鈩⑩€?technolo-
gy. The resulting transistor shows extremely low on-
resistance and minimal gate charge. The new Pow-
erFLAT鈩?package allow a significant reduction in
board space without compramising performance.
PowerFLAT鈩?5x5)
(Chip Scale Package)
INTERNAL SCHEMATIC DIAGRAM
APPLICATIONS
DC-DC CONVERTERS
BATTERY MANAGEMENT IN NOMADIC
EQUIPMENT
ABSOLUTE MAXIMUM RATINGS
Symbol
V
DS
V
DGR
V
GS
I
D
I
DM
( )
P
TOT
E
AS
(1)
T
stg
T
j
Parameter
Drain-source Voltage (V
GS
= 0)
Drain-gate Voltage (R
GS
= 20 k鈩?
Gate- source Voltage
Drain Current (continuous) at T
C
= 25擄C (*)
Drain Current (continuous) at T
C
= 100擄C
Drain Current (pulsed)
Total Dissipation at T
C
= 25擄C
Derating Factor
Single Pulse Avalanche Energy
Storage Temperature
Max. Operating Junction Temperature
Value
60
60
鹵 20
34
20
136
70
0.56
250
鈥?5 to 150
(1) Starting T
j
= 25擄C, I
D
= 17A, V
DD
= 42V
Unit
V
V
V
A
A
A
W
W/擄C
mJ
擄C
(鈥?Pulse width limited by safe operating area
(*) Current Limited by Wire Bonding is 20A
November 2002
1/6