(on) = 0.0055鈩?/div>
IMPROVED DIE-TO-FOOTPRINT RATIO
VERY LOW PROFILE PACKAGE
DESCRIPTION
This Power MOSFET is the second generation of
STMicroelectronics unique 鈥淪TripFET鈩⑩€?technolo-
gy. The resulting transistor shows extremely low on-
resistance and minimal gate charge. The new Pow-
erFLAT鈩?package allows a significant reduction in
board space without compromising performance.
PowerFLAT鈩?5x5)
(Chip Scale Package)
INTERNAL SCHEMATIC DIAGRAM
APPLICATIONS
s
DC-DC CONVERTERS
ABSOLUTE MAXIMUM RATINGS
Symbol
V
DS
V
DGR
V
GS
I
D
(#)
I
DM
( )
P
TOT
E
AS
(1)
T
stg
T
j
Parameter
Drain-source Voltage (V
GS
= 0)
Drain-gate Voltage (R
GS
= 20 k鈩?
Gate- source Voltage
Drain Current (continuos) at T
C
= 25擄C
Drain Current (continuos) at T
C
= 100擄C
Drain Current (pulsed)
Total Dissipation at T
C
= 25擄C
Derating Factor
Single Pulse Avalanche Energy
Storage Temperature
Max. Operating Junction Temperature
Value
30
30
鹵 16
28
17.5
112
80
0.64
2
鈥?5 to 150
(1) Starting T
j
= 25擄C, I
D
= 14A, V
DD
= 18V
Unit
V
V
V
A
A
A
W
W/擄C
J
擄C
(
q
) Pulse width limited by safe operating area
(#) Limited by Wire Bonding
November 2002
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