鈩?/div>
IMPROVED DIE-TO-FOOTPRINT RATIO
VERY LOW PROFILE PACKAGE (1mm MAX)
VERY LOW THERMAL RESISTANCE
VERY LOW GATE CHARGE
DESCRIPTION
This MOSFET series realized with STMicroelectronics
unique "STripFET鈩?quot; process has specifically been
designed to minimize input capacitance and gate charge.
It鈥檚 therefore suitable as primary switch in advanced high
efficiency, high frequency isolated DC-DC converter for
telecom
an
computer
application.
The
new
PowerFLAT鈩?package allows e significant reduction in a
board space without compromising performance.
PowerFLAT
鈩?6x5)
INTERNAL SCHEMATIC DIAGRAM
APPLICATIONS
s
HIGH-EFFICIENCY ISOLATED DC-DC
CONVERTERS
s
TELECOM AND BATTERY CHARGER
ADAPTOR
s
SYNCHRONOUS RECTIFICATION
Ordering Information
SALES TYPE
STL27N15
MARKING
L27N15
PACKAGE
PowerFLAT
PACKAGING
TAPE & REEL
ABSOLUTE MAXIMUM RATINGS
Symbol
V
DS
V
DGR
V
GS
I
D
I
D
I
DM(3)
P
tot(2)
P
tot(1)
dv/dt
(5)
T
stg
T
j
June 2003
This is preliminary information on a new product forseen to be developped. Details are subject to change without notice
Parameter
Drain-source Voltage (V
GS
= 0)
Drain-gate Voltage (R
GS
= 20 k鈩?
Gate- source Voltage
Drain Current (continuous) at T
C
= 25擄C (Steady State)
Drain Current (continuous) at T
C
= 100擄C
Drain Current (pulsed)
Total Dissipation at T
C
= 25擄C (Steady State)
Total Dissipation at T
C
= 25擄C
Derating Factor
Peak Diode Recovery voltage slope
Storage Temperature
Operating Junction Temperature
Value
150
150
鹵 20
6
4
24
4
80
0.03
TBD
-55 to 150
Unit
V
V
V
A
A
A
W
W
W/擄C
V/ns
擄C
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