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STK16C68-S45 Datasheet

  • STK16C68-S45

  • NVRAM (EEPROM Based)

  • 9頁

  • ETC

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STK16C68
8K x 8
AutoStorePlus鈩?/div>
nvSRAM
QuantumTrap鈩?/div>
CMOS
Nonvolatile Static RAM
FEATURES
鈥?Transparent Data Save on Power Down
鈥?Internal Capacitor Guarantees
AutoStore鈩?/div>
Regardless of Power-Down Slew Rate
鈥?Nonvolatile Storage without Battery Problems
鈥?Directly Replaces 8K x 8 Static RAM, Battery-
Backed RAM or EEPROM
鈥?20ns, 25ns, 35ns and 45ns Access Times
鈥?/div>
STORE
to EEPROM Initiated by Software or
AutoStorePlus鈩?/div>
on Power Down
鈥?/div>
RECALL
to SRAM Initiated by Software or
Power Restore
鈥?10mA Typical I
CC
at 200ns Cycle Time
鈥?Unlimited READ, WRITE and
RECALL
Cycles
鈥?1,000,000
STORE
Cycles to EEPROM
鈥?100-Year Data Retention over Full Industrial
Temperature Range
鈥?No Data Loss from Undershoot
鈥?Commercial and Industrial Temperatures
鈥?28-Pin 600 mil PDIP and 350 mil SOIC Packages
DESCRIPTION
The STK16C68 is a fast
SRAM
with a nonvolatile
EEPROM
element incorporated in each static memory
cell. The
SRAM
can be read and written an unlimited
number of times, while independent nonvolatile data
resides in
EEPROM
. Data transfers from the
SRAM
to
the
EEPROM
(the
STORE
operation) can take place
automatically on power down. An internal capacitor
guarantees the
STORE
operation regardless of power-
down slew rate. Transfers from the
EEPROM
to the
SRAM
(the
RECALL
operation) take place automatically
on restoration of power. Initiation of
STORE
and
RECALL
cycles can also be controlled by entering con-
trol sequences on the
SRAM
inputs. The STK16C68 is
pin-compatible with 8k x 8
SRAM
s and battery-backed
SRAM
s, allowing direct substitution while enhancing
performance. The STK12C68, which uses an external
capacitor, and the STK15C68, which uses charge
stored in system capacitance, are alternatives for sys-
tems needing
AutoStore鈩?/div>
operation.
BLOCK DIAGRAM
EEPROM ARRAY
128 x 512
V
CC
STORE/
RECALL
CONTROL
PIN CONFIGURATIONS
NC
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DQ
0
DQ
1
DQ
2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A
5
ROW DECODER
A
6
A
7
A
8
A
9
A
11
A
12
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
STORE
STATIC RAM
ARRAY
128 x 512
RECALL
POWER
CONTROL
INTERNAL
CAPACITOR
V
CC
W
NC
A
8
A
9
A
11
G
A
10
E
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
28 - 600 PDIP
28 - 350 SOIC*
*see order info
INPUT BUFFERS
COLUMN I/O
COLUMN DEC
SOFTWARE
DETECT
A
0
- A
12
PIN NAMES
A
0
- A
12
W
Address Inputs
Write Enable
Data In/Out
Chip Enable
Output Enable
Power (+ 5V)
Ground
A
0
A
1
A
2
A
3
A
4
A
10
DQ
0
- DQ
7
G
E
W
E
G
V
CC
V
SS
July 1999
4-73

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