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STH8NA80 Datasheet

  • STH8NA80

  • N - CHANNEL ENHANCEMENT MODE POWER MOS TRANSISTORS

  • 49.08KB

  • 6頁(yè)

  • STMICROELECTRONICS   STMICROELECTRONICS

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廬
STW8NA80
STH8NA80FI
N - CHANNEL ENHANCEMENT MODE
POWER MOS TRANSISTORS
PRELIMINARY DATA
TYPE
STW 8NA80
STH8NA80F I
s
s
s
s
s
s
s
V
DSS
800 V
800 V
R
DS(on)
< 1.50
鈩?/div>
< 1.50
鈩?/div>
I
D
7.2 A
4.5 A
TYPICAL R
DS(on)
= 1.3
鈩?/div>
鹵
30V GATE TO SOURCE VOLTAGE RATING
100% AVALANCHE TESTED
REPETITIVE AVALANCHE DATA AT 100
o
C
LOW INTRINSIC CAPACITANCES
GATE GHARGE MINIMIZED
REDUCED THRESHOLD VOLTAGE SPREAD
1
2
3
2
1
3
DESCRIPTION
This series of POWER MOSFETS represents the
most advanced high voltage technology. The op-
timized cell layout coupled with a new proprietary
edge termination concur to give the device low
RDS(on) and gate charge, unequalled rug-
gedness and superior switching performance.
APPLICATIONS
s
HIGH CURRENT, HIGH SPEED SWITCHING
s
SWITCH MODE POWER SUPPLIES (SMPS)
s
DC-AC CONVERTERS FOR WELDING
EQUIPMENT AND UNINTERRUPTIBLE
POWER SUPPLIES AND MOTOR DRIVE
ABSOLUTE MAXIMUM RATINGS
Symb ol
Parameter
TO-247
ISOWATT218
INTERNAL SCHEMATIC DIAGRAM
Valu e
STW 8NA80
ST H8NA80FI
800
800
鹵
30
7.2
4.5
28.8
175
1.4
錚?/div>
-65 to 150
150
4.5
2.8
28.8
70
0.56
4000
Unit
V
DS
V
DGR
V
GS
I
D
I
D
I
DM
(鈥?
P
tot
V
ISO
T
s tg
T
j
Drain-source Voltage (V
GS
= 0)
Drain- gate Voltage (R
GS
= 20 k鈩?
G ate-source Voltage
Drain Current (continuous) at T
c
= 25
o
C
Drain Current (continuous) at T
c
= 100
o
C
Drain Current (pulsed)
T otal Dissipation at T
c
= 25
o
C
Derating Factor
Insulation W ithstand Voltage (DC)
Storage T emperature
Max. O perating Junct ion T emperature
V
V
V
A
A
A
W
W/
o
C
V
o
o
C
C
(鈥? Pulse width limited by safe operating area
October 1998
1/6

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