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STG3685 Datasheet

  • STG3685

  • LOW VOLTAGE 0.5? MAX DUAL SPDT SWITCH, SINGLE ENABLE WITH BR...

  • 10頁

  • STMICROELECTRONICS   STMICROELECTRONICS

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STG3685
LOW VOLTAGE 0.5鈩?MAX DUAL SPDT SWITCH,
SINGLE ENABLE WITH BREAK BEFORE MAKE FEATURE
PRELIMINARY DATA
I
I
I
I
I
I
I
HIGH SPEED:
t
PD
= 0.3ns (TYP.) at V
CC
= 3.0V
t
PD
= 0.4ns (TYP.) at V
CC
= 2.3V
ULTRA LOW POWER DISSIPATION:
I
CC
= 0.2碌A(chǔ) (MAX.) at T
A
= 85擄C
LOW "ON" RESISTANCE V
I
= 0V:
R
ON
= 0.4鈩?(MAX. T
A
= 25擄C) at V
CC
= 4.2V
R
ON
= 0.5鈩?(MAX. T
A
= 25擄C) at V
CC
= 3.0V
R
ON
= 0.6鈩?(MAX. T
A
= 25擄C) at V
CC
= 2.3V
WIDE OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 1.4V to 4.3V SINGLE SUPPLY
4.3V TOLERANT AND 1.8V COMPATIBLE
THRESHOLD ON DIGITAL CONTROL INPUT
at V
CC
= 2.3 to 4.3V
LATCH-UP PERFORMANCE EXCEEDS
300mA (JESD 17)
ESD PERFORM. (ANALOG CHAN. vs GND):
HBM > 4KV (MIL STD 883 method 3015)
Flip-Chip
Table 1: Order Codes
PACKAGE
Flip-Chip9
T&R
STG3685BJR
DESCRIPTION
The STG3685 is an high-speed CMOS DUAL
ANALOG S.P.D.T. (Single Pole Dual Throw)
SWITCH or DUAL 2:1 Multiplexer/Demultiplexer
Bus Switch fabricated in silicon gate C
2
MOS
technology. It is designed to operate from 1.4V to
4.3V, making this device ideal for portable
applications.
It offers very low ON-Resistance (<0.5鈩? at
V
CC
=3.0V. The IN input is provided to control the
switches. The switches nS1 are ON (they are
connected to common Ports Dn) when the IN input
is held high and OFF (high impedance state exists
between the two ports) when IN is held low; the
switches nS2 are ON (they are connected to
common Ports Dn) when the IN input is held low
and OFF (high impedance state exists between
the two ports) when IN is held high. Additional key
features are fast switching speed, Break Before
Make Delay Time and Ultra Low Power
Consumption. All inputs and outputs are equipped
with protection circuits against static discharge,
giving them ESD immunity and transient excess
voltage. It鈥檚 available in the commercial
temperature range Flip-chip package with Epoxy
Protection.
Figure 1: Pin Connection
(Top Through View)
And Schematic Circuit
July 2005
Rev. 2
1/10
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

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