STG3684
LOW VOLTAGE 0.5鈩?MAX DUAL SPDT SWITCH
WITH BREAK BEFORE MAKE FEATURE
s
s
s
s
s
s
HIGH SPEED:
t
PD
= 0.3ns (TYP.) at V
CC
= 3.0V
t
PD
= 0.4ns (TYP.) at V
CC
= 2.3V
ULTRA LOW POWER DISSIPATION:
I
CC
= 0.2碌A(chǔ) (MAX.) at T
A
= 85擄C
LOW "ON" RESISTANCE V
IN
= 0V:
R
ON
= 0.5鈩?(MAX. T
A
= 25擄C) at V
CC
= 2.7
R
ON
= 0.8鈩?(MAX. T
A
= 25擄C) at V
CC
= 2.3V
R
ON
= 3.0鈩?(MAX. T
A
= 25擄C) at V
CC
= 1.8V
WIDE OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 1.65V to 4.3V SINGLE SUPPLY
4.3V TOLERANT AND 1.8V COMPATIBLE
THRESHOLD ON DIGITAL CONTROL INPUT
at V
CC
= 2.3 to 3.0V
LATCH-UP PERFORMANCE EXCEEDS
300mA (JESD 17)
QFN
ORDER CODES
PACKAGE
QFN
T&R
STG3684QTR
DESCRIPTION
The STG3684 is an high-speed CMOS DUAL
ANALOG S.P.D.T. (Single Pole Dual Throw)
SWITCH or DUAL 2:1 Multiplexer/Demultiplexer
Bus Switch fabricated in silicon gate C
2
MOS
technology. It is designed to operate from 1.65V to
4.3V, making this device ideal for portable
applications.
It offers very low ON-Resistance (<0.5
鈩?/div>
) at
V
CC
=3.0V. The nIN inputs are provided to control
the switches. The switches nS1 are ON (they are
PIN CONNECTION
connected to common Ports Dn) when the nIN
input is held high and OFF (high impedance state
exists between the two ports) when nIN is held
low; the switches nS2 are ON (they are connected
to common Ports Dn) when the nIN input is held
low and OFF (high impedance state exists
between the two ports) when IN is held high.
Additional key features are fast switching speed,
Break Before Make Delay Time and Ultra Low
Power Consumption. All inputs and outputs are
equipped with protection circuits against static
discharge, giving them ESD immunity and
transient excess voltage. It鈥檚 available in the
commercial temperature range in the QFN
package.
May 2004
Rev. 2
1/11
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