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STE2004 Datasheet

  • STE2004

  • 102 X 65 SINGLE CHIP LCD CONTROLLER/DRIVER

  • 741.51KB

  • STMicroelectronics   STMicroelectronics

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STE2004
102 X 65 SINGLE CHIP LCD CONTROLLER / DRIVER
1
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FEATURES
102 x 65 bits Display Data RAM
Programmable MUX rate
Programmable Frame Rate
X,Y Programmable Carriage Return
Dual Partial Display Mode
Row by Row Scrolling
N-Line Inversion
Automatic data RAM Blanking procedure
Selectable Input Interface:
鈥?I
2
C Bus Fast and Hs-mode (read and write)
鈥?68000 & 8080 Parallel Interfaces (read and write)
鈥?3-lines and 4-lines SPI Interface (read and write)
鈥?3-lines 9 bit Serial Interface (read and write)
Fully Integrated Oscillator requires no external
components
CMOS Compatible Inputs
Fully Integrated Configurable LCD bias voltage
generator with:
鈥?Selectable multiplication factor (up to 5
X
)
鈥?Effective sensing for High Precision Output
鈥?Eight selectable temperature compensation
coefficients
Designed for chip-on-glass (COG) applications.
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Low Power Consumption, suitable for battery
operated systems
Logic Supply Voltage range from 1.7 to 3.6V
High Voltage Generator Supply Voltage range
from 1.75 to 4.5V
Display Supply Voltage range from 4.5 to 14.5V
Backward Compatibility with STE2001/2
2
DESCRIPTION
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The STE2004 is a low power CMOS LCD control-
ler driver. Designed to drive a 65 rows by 102 col-
umns graphic display, it provides all necessary
functions in a single chip, including on-chip LCD
supply and bias voltages generators, resulting in a
minimum of externals components and in a very
low power consumption.
STE2004 features six standard interfaces (3-lines
Serial, 3-lines SPI, 4-lines SPI, 68000 Parallel,
8080 parallel & I
2
C) for ease of interfacing with the
host micro-controller
Table 1. Order Codes
Part Numbers
STE2004DIE1
STE2004DIE2
Type
Bumped Wafers
Bumped Dice on Waffle Pack
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Figure 1. Block Diagram
CO to C101
R0 to R64
OSC_IN
OSC_OUT
FR_IN
FR_OUT
OSC
MASTER
SLAVE SYNC
BIAS VOLTAGE
GENERATOR
TIMING
GENERATOR
CLOCK
COLUMN
DRIVERS
ROW
DRIVERS
DATA
LATCHES
SHIFT
REGISTER
VSENSE SLAVE
VLCD
VLCDSENSE
RES
VSSAUX
VDD1,2
V
SS
SEL1,2
SEL 0
DATA
REGISTER
INSTRUCTION
REGISTER
RESET
HIGH VOLTAGE
GENERATOR
65 x 102
RAM
SCROLL
LOGIC
TEST
TEST_MODE
TEST_VREF
ICON_MODE
EXT
DISPLAY
CONTROL
LOGIC
I2C BUS
9 Bit SERIAL
3 & 4 Line SPI
Parallel 8080
Parallel 68K
SEL 1
SEL 2
SA1 SAO SDOUT SCLK/SCL SDIN/SDA_IN SDA_OUT DB0 E/WR R/W- RD
to
DB7
D/C
CS
LR0047
July 2004
Rev. 4
1/66

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