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STE110NA20 Datasheet

  • STE110NA20

  • N - CHANNEL ENHANCEMENT MODE FAST POWER MOS TRANSISTOR

  • 8頁

  • STMICROELECTRONICS   STMICROELECTRONICS

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STE110NA20
N - CHANNEL ENHANCEMENT MODE
FAST POWER MOS TRANSISTOR
PRELIMINARY DATA
TYPE
ST E110NA20
V
DSS
200 V
R
DS(on)
< 0.019
鈩?/div>
I
D
110 A
s
s
s
s
s
s
s
s
s
TYPICAL R
DS(on)
= 0.015
鈩?/div>
HIGH CURRENT POWER MODULE
AVALANCHE RUGGED TECHNOLOGY
VERY LARGE SOA - LARGE PEAK POWER
CAPABILITY
EASY TO MOUNT
SAME CURRENT CAPABILITY FOR THE
TWO SOURCE TERMINALS
EXTREMELY LOW Rth (Junction to case)
VERY LOW INTERNAL PARASITIC
INDUCTANCE
ISOLATED PACKAGE UL RECOGNIZED
ISOTOP
APPLICATIONS
s
SMPS & UPS
s
MOTOR CONTROL
s
WELDING EQUIPMENT
s
OUTPUT STAGE FOR PWM, ULTRASONIC
CIRCUITS
INTERNAL SCHEMATIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol
V
DS
V
DGR
V
GS
I
D
I
D
I
DM
(鈥?
P
to t
Parameter
Drain-source Voltage (V
GS
= 0)
Drain- gate Voltage (R
GS
= 20 k鈩?
Gate-source Voltage
Drain Current (continuous) at T
c
= 25
o
C
Drain Current (continuous) at T
c
= 100 C
Drain Current (pulsed)
Total Dissipation at T
c
= 25 C
Derating Factor
T
st g
T
j
V
ISO
Storage Temperature
Max. Operating Junction Temperature
Insulation Withhstand Voltage (AC-RMS)
o
o
Value
200
200
鹵
30
110
73
440
450
3.6
-55 to 150
150
2500
Unit
V
V
V
A
A
A
W
W/ C
o
o
o
C
C
V
(鈥? Pulse width limited by safe operating area
March 1996
1/8

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