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STE10/STE100A Datasheet

  • STE10/STE100A

  • STE10/100A - PCI 10/100 ETHERNET CONTROLLER WITH PHY DATASHE...

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STE10/100A
PCI 10/100 ETHERNET CONTROLLER
WITH INTEGRATED PHY (3.3V)
1.0 DESCRIPTION
The STE10/100A is a high performance PCI Fast
Ethernet controller with integrated physical layer in-
terface for 10BASE-T and 100BASE-TX application.
It was designed with advanced CMOS technology to
provide glueless 32-bit bus master interface for PCI
bus, boot ROM interface, CSMA/CD protocol for Fast
Ethernet, as well as the physical media interface for
100BASE-TX of IEEE802.3u and 10BASE-T of
IEEE802.3. The auto-negotiation function is also
supported for speed and duplex detection.
The STE10/100A provides both half-duplex and full-
duplex operation, as well as support for full-duplex
flow control. It provides long FIFO buffers for trans-
mission and receiving, and early interrupt mecha-
nism to enhance performance. The STE10/100A also
supports ACPI and PCI compliant power manage-
ment function.
2.0 FEATURES
2.1 Industry standard
s
s
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PQFP128 (14x20x2.7mm)
ORDERING INFO:
STE10/100A - Commercial Temp version
STE10/100E - Industrial Temp version
PCI bus interface Rev. 2.2 compliant
ACPI and PCI power management standard
compliant
Support for PC99 wake on LAN
Provides 32-bit PCI bus master data transfer at
PCI clocks of 20-33 MHz
Provides writeable EEPROM/ Boot Rom
Interface
Provides independent transmission and
receiving FIFOs, each 2k bytes long
Supports big endian or little endian byte
ordering
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IEEE802.3u 100BASE-TX and IEEE802.3
10BASE-T compliant
Support for IEEE802.3x flow control
IEEE802.3u Auto-Negotiation support for
10BASE-T and 100BASE-TX
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Figure 1. STE10/100A Block Diagram
November 2002
REVISION: A07
Details are subject to change without notice.
1/66

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