STDL150
S MSUNG
ELECTRONICS
STDL150 Standard Cell
0.13um System-On-Chip ASIC
March 2002, V1.0
Features
Analog cores
Analog Interface
- L
drawn
= 0.13um
1.5/2.5/3.3V
Device
1.5/2.5/3.3V
- Up to 45.8 million gates
Interface
- Power dissipation: 13nW/MHz@1.5V, 2SL, ND2
5.0V
- Gate Delay: 69ps@1.5V, 2SL, ND2
Device
5.0V CMOS/TTL
- 1.5/2.5/3.3V drive and 5V tolerant I/O
- Low-power compiled SRAM/ROM with best-density
- 1.5V and 3.3V ADC,DAC and PLLs
- ARM920T/ARM940T, TeakLite/TeakHigh-density
NOTE:
2.5V and 3.3V cannot be used simultaneously.
1.5/2.5/3.3V
5.0V
Tolerant
USB
USB Bus
Description
STDL150 is one of the Samsung ASIC library,
which consists of standard cell products imple-
mented in a 0.13um technology. STDL150 utilizes
seven layers of interconnect metal having metal 4,
5, 6 and 7 layer options for products. STDL150 is
diverse application speci鏗乧 digital and analog IPs
for system-on-chip(SOC) application. Samsung
provides a full range of products to address the
challenges of producing portable devices that take
advantage of SOC integration.
STDL150 which reduced power dissipation and
system cost by merging the logic and IPs as a
whole and connecting internally from logic to
memory data bus is ideal for low-power products
such as HHP, PDA and Mobile.
STDL150 supports up to 45.8 million gates counts
of logic providing 85% of usable gate. Gate delay
is 30%~40% slower than that of STD150, 0.13um
library. Logic density is exactly same as that of
STD150.
STDL150 also supports fully user-con鏗乬urable
compiled memory elements for low-power with
minimum area loss. In STDL150, the density of
compiled memory is 20% less than that of
STD150. Each element is provided as a compiler.
For high-capacity memory solution in SOC
design, the repairable memory containing redun-
dancy scheme is also provided as a compiler.
Variety of IPs are provided in STDL150 family
including
- Processor Cores :
ARM7T/ARM9T/ARM940T/ARM920T/
ARM946E/ARM926EJ/ARM1020E/ETM7/
ETM9 from ARM, TeakLite/TEAK from
DSPG
- Memories
Low-power compiled SRAM
High-density compiled ROM/Registor 鏗乴e,
Low-power repairable SRAM with
redundancy
- Analog Cores :
ADC, DAC, PLL
- IO IPs :
USB, PCI-X, ATA-6, LVDS, SSTL2, HSTL,
PECL
Samsung design methodology offers an compre-
hensive timing driven design 鏗俹w including auto-
mated time budgeting, tight 鏗俹orplan synthesis
integration, powerful timing analysis and timing
driven layout. Its advanced characterization 鏗俹w
provides accurate timing data and robust delay
models for a 0.13um very deep-submicron tech-
nology. Static veri鏗乧ation methods such as static
timing analysis and formal equivalence checking
provide an effective veri鏗乧ation methodology with
a variety of simulators. Samsung DFT methodol-
ogy supports scan design, BIST and JTAG bound-
ary scan. Samsung provides a full set of test-
ready IPs with an ef鏗乧ient core test integration
methodology.
Samsung ASIC
V
V
STDL150
(1.5V)
PCI
PCI-X
Hot Swap PCI
PCI Bus
SSTL2
PECL
HSTL
LVDS
High speed
Devices
1
1
2
3
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