鈩?/div>
@ 4.5V
OPTIMAL R
DS
(on) x Qg TRADE-OFF @ 4.5V
CONDUCTION LOSSES REDUCED
SWITCHING LOSSES REDUCED
LOW THRESHOLD DRIVE
THROUGH-HOLE IPAK (TO-251) POWER
PACKAGE IN TUBE (SUFFIX 鈥?1")
SURFACE-MOUNTING DPAK (TO-252)
POWER PACKAGE IN TAPE & REEL
(SUFFIX 鈥淭4")
3
2
1
IPAK
TO-251
(Suffix 鈥?1鈥?
DPAK
TO-252
(Suffix 鈥淭4鈥?
3
1
DESCRIPTION
This application specific Power MOSFET is the third
genaration of STMicroelectronis unique "Single Feature
Size鈩?quot; strip-based process. The resulting transistor
shows the best trade-off between on-resistance and gate
charge. When used as high and low side in buck
regulators, it gives the best performance in terms of both
conduction and switching losses. This is extremely
important for motherboards where fast switching and
high efficiency are of paramount importance.
INTERNAL SCHEMATIC DIAGRAM
APPLICATIONS
s
SPECIFICALLY DESIGNED AND OPTIMISED
FOR HIGH EFFICIENCY DC/DC
CONVERTERS
ABSOLUTE MAXIMUM RATINGS
Symbol
V
DS
V
DGR
V
GS
I
D
I
D
I
DM
(鈥?
P
tot
E
AS (1)
T
stg
T
j
February 2002
.
Parameter
Drain-source Voltage (V
GS
= 0)
Drain-gate Voltage (R
GS
= 20 k鈩?
Gate- source Voltage
Drain Current (continuos) at T
C
= 25擄C
Drain Current (continuos) at T
C
= 100擄C
Drain Current (pulsed)
Total Dissipation at T
C
= 25擄C
Derating Factor
Single Pulse Avalanche Energy
Storage Temperature
Max. Operating Junction Temperature
Value
30
30
鹵 16
35
25
140
50
0.33
300
-55 to 175
(1) Starting T
j
= 25
o
C, I
D
= 17.5 A, V
DD
= 24 V
Unit
V
V
V
A
A
A
W
W/擄C
mJ
擄C
(鈥?
Pulse width limited by safe operating area.
1/10