STB85NF3LL Datasheet

IC型號：
STB85NF3LL
PDF描述：
N-CHANNEL 30V - 0.006ohm - 85A D2PAK LOW GATE CHARGE STripFE...
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431.31KB
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9頁
芯片廠家：
STMICROELECTRONICS

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STB85NF3LL

N-CHANNEL 30V - 0.006鈩?- 85A D

PAK

LOW GATE CHARGE STripFET鈩I POWER MOSFET

TYPE

STB85NF3LL

DSS

30 V

DS(on)

< 0.008

鈩?/div>

85 A

TYPICAL R

(on) = 0.0075鈩?(@4.5V)

OPTIMAL R

(on) x Qg TRADE-OFF @4.5V

CONDUCTION LOSSES REDUCED

SWITCHING LOSSES REDUCED

ADD SUFFIX 鈥淭4鈥?FOR ORDERING IN TAPE &

REEL

PAK

DESCRIPTION

This application specific Power MOSFET is the third

genaration of STMicroelectronics unique 鈥?Single

Feature Size鈥?strip-based process. The resulting

transistor shows the best trade-off between on-re-

sistance and gate charge. When used as high and

low side in buck regulators, it gives the best perfor-

mance in terms of both conduction and switching

losses. This is extremely important for mother-

boards where fast switching and high efficiency are

of paramount importance.

APPLICATIONS

SPECIFICALLY DESIGNED AND OPTIMISED

FOR HIGH EFFICIENCY CPU CORE DC/DC

CONVERTERS

ABSOLUTE MAXIMUM RATINGS

Symbol

DGR

GSM

(

)

TOT

stg

Parameter

Drain-source Voltage (V

= 0)

Drain-gate Voltage (R

= 20 k鈩?

Gate- source Voltage

Gate-source Voltage Pulsed

鈮?0碌s;

duty cycle 25%; T

鈮?/div>

150擄C)

Drain Current (continuos) at T

= 25擄C

Drain Current (continuos) at T

= 100擄C

Drain Current (pulsed)

Total Dissipation at T

= 25擄C

Derating Factor

Storage Temperature

Max. Operating Junction Temperature

Value

鹵 16

鹵 20

340

110

0.73

鈥?5 to 175

175

Unit

W/擄C

擄C

INTERNAL SCHEMATIC DIAGRAM

(

) Pulse width limited by safe operating area

November 2001

1/9

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STB85NF3LL Datasheet

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