鈩?/div>
I
D
85 A
TYPICAL R
DS
(on) = 0.0075鈩?(@4.5V)
OPTIMAL R
DS
(on) x Qg TRADE-OFF @4.5V
CONDUCTION LOSSES REDUCED
SWITCHING LOSSES REDUCED
ADD SUFFIX 鈥淭4鈥?FOR ORDERING IN TAPE &
REEL
3
1
D
2
PAK
DESCRIPTION
This application specific Power MOSFET is the third
genaration of STMicroelectronics unique 鈥?Single
Feature Size鈥?strip-based process. The resulting
transistor shows the best trade-off between on-re-
sistance and gate charge. When used as high and
low side in buck regulators, it gives the best perfor-
mance in terms of both conduction and switching
losses. This is extremely important for mother-
boards where fast switching and high efficiency are
of paramount importance.
APPLICATIONS
s
SPECIFICALLY DESIGNED AND OPTIMISED
FOR HIGH EFFICIENCY CPU CORE DC/DC
CONVERTERS
ABSOLUTE MAXIMUM RATINGS
Symbol
V
DS
V
DGR
V
GS
V
GSM
I
D
I
D
I
DM
(
l
)
P
TOT
T
stg
T
j
Parameter
Drain-source Voltage (V
GS
= 0)
Drain-gate Voltage (R
GS
= 20 k鈩?
Gate- source Voltage
Gate-source Voltage Pulsed
(t
p
鈮?0碌s;
duty cycle 25%; T
j
鈮?/div>
150擄C)
Drain Current (continuos) at T
C
= 25擄C
Drain Current (continuos) at T
C
= 100擄C
Drain Current (pulsed)
Total Dissipation at T
C
= 25擄C
Derating Factor
Storage Temperature
Max. Operating Junction Temperature
Value
30
30
鹵
16
鹵
20
85
60
340
110
0.73
鈥?5 to 175
175
Unit
V
V
V
V
A
A
A
W
W/擄C
擄C
擄C
INTERNAL SCHEMATIC DIAGRAM
(
q
) Pulse width limi ted by safe operating area
November 2001
1/9
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