(on) = 0.008鈩?/div>
TYPICAL Qg= 35 nC @10V
OPTIMAL R
DS
(on) x Qg TRADE-OFF
CONDUCTION LOSSES REDUCED
SWITCHING LOSSES REDUCED
ADD SUFFIX 鈥淭4鈥?FOR ORDERING IN TAPE &
REEL
3
1
D2PAK
DESCRIPTION
This application specific Power MOSFET is the third
genaration of STMicroelectronics unique 鈥?Single
Feature Size鈥?strip-based process. The resulting
transistor shows the best trade-off between on-re-
sistance and gate charge. When used as high and
low side in buck regulators, it gives the best perfor-
mance in terms of both conduction and switching
losses. This is extremely important for mother-
boards where fast switching and high efficiency are
of paramount importance.
APPLICATIONS
s
SPECIFICALLY DESIGNED AND OPTIMISED
FOR HIGH EFFICIENCY CPU CORE DC/DC
CONVERTERS
s
AUTOMOTIVE
ABSOLUTE MAXIMUM RATINGS
Symbol
V
DS
V
DGR
V
GS
I
D
I
D
I
DM
(
q
)
P
TOT
dv/dt (1)
T
stg
T
j
April 2001
Parameter
Drain-source Voltage (V
GS
= 0)
Drain-gate Voltage (R
GS
= 20 k鈩?
Gate- source Voltage
Drain Current (continuos) at T
C
= 25擄C
Drain Current (continuos) at T
C
= 100擄C
Drain Current (pulsed)
Total Dissipation at T
C
= 25擄C
Derating Factor
Peak Diode Recovery voltage slope
Storage Temperature
Max. Operating Junction Temperature
INTERNAL SCHEMATIC DIAGRAM
Value
30
30
鹵
20
70
50
280
100
0.67
4
鈥?0 to 175
175
(1) I
SD
鈮?0A,
di/dt
鈮?90A/碌s,
V
DD
鈮?/div>
V
(BR)DSS
, T
j
鈮?/div>
T
JMAX.
Unit
V
V
V
A
A
A
W
W/擄C
V/ns
擄C
擄C
1/9
(
q
) Pulse width limi ted by safe operating area
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