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STB70NF02LT4 Datasheet

  • STB70NF02LT4

  • TRANSISTOR | MOSFET | N-CHANNEL | 20V V(BR)DSS | 70A I(D) | ...

  • 7頁

  • ETC

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N-CHANNEL 20V - 0.006
鈩?/div>
- 70A D
2
PAK
LOW GATE CHARGE STripFET鈩?II POWER MOSFET
TYPE
STB70NF02L
s
s
s
s
s
STB70NF02L
PRELIMINARY DATA
V
DSS
20 V
R
DS(on)
<0.009鈩?/div>
I
D
70 A
TYPICAL R
DS
(on) = 0.016
鈩?/div>
TYPICAL Q
g
= 36 nC @ 10 V
OPTIMAL R
DS(on)
x Qg TRADE-OFF
CONDUCTION LOSSES REDUCED
SWITCHING LOSSES REDUCED
3
1
DESCRIPTION
This application specific Power MOSFET is the third
genaration of STMicroelectronis unique 鈥漇ingle Feature
Size鈩?鈥?strip-based process. The resulting transistor
shows the best trade-off between on-resistance and gate
charge. When used as high and low side in buck
regulators, it gives the best performance in terms of both
conduction and switching losses. This is extremely
important for motherboards where fast switching and
high efficiency are of paramount importance.
D
2
PAK
TO-263
(Suffix 鈥淭4鈥?
ADD SUFFIX 鈥淭4鈥?FOR ORDERING IN TAPE & REEL
INTERNAL SCHEMATIC DIAGRAM
APPLICATIONS
s
SPECIFICALLY DESIGNED AND OPTIMISED
FOR HIGH EFFICIENCY CPU CORE DC/DC
CONVERTERS
ABSOLUTE MAXIMUM RATINGS
Symbol
V
DS
V
DGR
V
GS
I
D
I
D
I
DM
(鈥?
P
tot
T
stg
T
j
March 2002
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Parameter
Drain-source Voltage (V
GS
= 0)
Drain-gate Voltage (R
GS
= 20 k鈩?
Gate- source Voltage
Drain Current (continuous) at T
C
= 25擄C
Drain Current (continuous) at T
C
= 100擄C
Drain Current (pulsed)
Total Dissipation at T
C
= 25擄C
Derating Factor
Storage Temperature
Max. Operating Junction Temperature
Value
20
20
鹵
18
70
50
280
100
0.67
-65 to 175
175
Unit
V
V
V
A
A
A
W
W/擄C
擄C
擄C
1/7
(鈥?
Pulse width limit ed by safe operating area

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