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STB50NE10LT4 Datasheet

  • STB50NE10LT4

  • TRANSISTOR | MOSFET | N-CHANNEL | 100V V(BR)DSS | 50A I(D) |...

  • 6頁(yè)

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N-CHANNEL 100V - 0.020
鈩?/div>
- 50A D
2
PAK
STripFET鈩?POWER MOSFET
PRELIMINARY DATA
TYPE
STB50NE10L
s
s
s
s
s
STB50NE10L
V
DSS
100 V
R
DS(on)
<0.025
鈩?/div>
I
D
50 A
s
TYPICAL R
DS
(on) = 0.020鈩?/div>
EXCEPTIONAL dv/dt CAPABILITY
100% AVALANCHE TESTED
LOW GATE CHARGE 100
o
C
APPLICATION ORIENTED
CHARACTERIZATION
FOR THROUGH-HOLE VERSION CONTACT
SALES OFFICE
3
1
D
2
PAK
TO-263
(suffix鈥淭4鈥?
DESCRIPTION
This Power Mosfet is the latest development of
STMicroelectronis unique 鈥漇ingle Feature Size鈩?鈥?/div>
strip-based process. The resulting transistor
shows extremely high packing density for low on-
resistance, rugged avalanche characteristics and
less critical alignment steps therefore a remark-
able manufacturing reproducibility.
APPLICATIONS
s
HIGH CURRENT, HIGH SPEED SWITCHING
s
SOLENOID AND RELAY DRIVERS
s
MOTOR CONTROL, AUDIO AMPLIFIERS
s
DC-DC & DC-AC CONVERTERS
s
AUTOMOTIVE ENVIRONMENT
ABSOLUTE MAXIMUM RATINGS
Symbol
V
DS
V
DGR
V
GS
I
D
I
D
I
DM
(鈥?
P
tot
dv/dt
(1)
T
stg
T
j
Parameter
Drain-source Voltage (V
GS
= 0)
Drain-gate Voltage (R
GS
= 20 k鈩?
Gate- source Voltage
Drain Current (continuos) at T
C
= 25擄C
Drain Current (continuos) at T
C
= 100擄C
Drain Current (pulsed)
Total Dissipation at T
C
= 25擄C
Derating Factor
Peak Diode Recovery voltage slope
Storage Temperature
Max. Operating Junction Temperature
INTERNAL SCHEMATIC DIAGRAM
Value
100
100
鹵20
50
35
200
150
1
6
鈥?5 to 175
175
(1)
Unit
V
V
V
A
A
A
W
W/擄C
V/ns
擄C
擄C
(
鈥?/div>
)Pulse width limited by safe operating area.
I
SD
鈮?0A,
di/dt
鈮?00A/碌s,
V
DD
鈮?/div>
V
(BR)DSS
, T
j
鈮?/div>
T
JMAX.
November 2000
This is preliminary data new product in development or undergoing evaluation. Details are subject to change without notice.
1/6

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