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STA003T Datasheet

  • STA003T

  • MPEG 2.5 LAYER III AUDIO DECODER

  • 302.36KB

  • 32頁

  • STMICROELECTRONICS   STMICROELECTRONICS

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STA003T
MPEG 2.5 LAYER III AUDIO DECODER
SINGLE CHIP MPEG2 LAYER 3 DECODER
SUPPORTING:
- All features specified for Layer III in ISO/IEC
11172-3 (MPEG 1 Audio) except 44.1KHz
Audio
- All features specified for Layer III 2 channels
in ISO/IEC13818-3.2 (MPEG 2 Audio) except
22.05KHz Audio
- Lower sampling frequencies syntax extension,
(not specified by ISO) called MPEG 2.5
except 11.025KHz Audio
DECODES LAYER III STEREO CHANNELS,
DUAL
CHANNEL,
SINGLE
CHANNEL
(MONO)
SUPPORTING THE MPEG 1 & 2 SAMPLING
FREQUENCIES AND THE EXTENSION TO
MPEG 2.5:
48, 32, 24, 16, 12, 8 KHz
ACCEPTS MPEG 2.5 LAYER III ELEMEN-
TARY COMPRESSED BITSTREAM WITH
DATA RATE FROM 8 Kbit/s UP TO 128 Kbit/s
DIGITAL VOLUME CONTROL
DIGITAL BASS & TREBLE CONTROL
SERIAL BITSTREAM INPUT INTERFACE
ANCILLARY DATA EXTRACTION VIA I2C IN-
TERFACE.
SERIAL PCM OUTPUT INTERFACE (I
2
S
AND OTHER FORMATS)
PLL FOR INTERNAL CLOCK AND FOR OUT-
PUT PCM CLOCK GENERATION
LOW POWER DATA ELABORATION FOR
POWER CONSUMPTION OPTIMISATION
CRC CHECK AND SYNCHRONISATION ER-
ROR DETECTION WITH SOFTWARE INDI-
CATORS
I
2
C CONTROL BUS
LOW POWER 3.3V CMOS TECHNOLOGY
14.72MHz EXTERNAL INPUT CLOCK OR
BUILT-IN XTAL OSCILLATOR
SO28
APPLICATIONS
STARMAN SATELLITE RADIO RECEIVER
DESCRIPTION
The STA003T is a fully integrated high flexibility
MPEG Layer III Audio Decoder, capable of de-
coding Layer III compressed elementary streams,
as specified in MPEG 1 and MPEG 2 ISO stand-
ards. The device decodes also elementary streams
compressed by using low sampling rates, as speci-
fied by MPEG 2.5.
STA003T receives the input data through a Serial
Input Interface. The decoded signal is a stereo,
mono, or dual channel digital output that can be
sent directly to a D/A converter, by the PCM Out-
put Interface. This interface is software program-
mable to adapt the STA003T digital output to the
most common DACs architectures used on the
market.
The functional STA003T chip partitioning is de-
scribed in Fig.1.
January 2002
1/32

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