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ST92195C/D

48-96 Kbyte ROM HCMOS MCU WITH

ON-SCREEN DISPLAY AND TELETEXT DATA SLICER

s

s

s

s

s

s

s

s

s

s

s

s

s

s

s

s

s

s

s

s

Register File based 8/16 bit Core Architecture

with RUN, WFI, SLOW and HALT modes

0擄C to +70擄C operating temperature range

Up to 24 MHz. operation @ 5V鹵10%

Min. instruction cycle time: 165ns at 24 MHz.

48, 56, 64, 84 or 96 Kbytes ROM

256 bytes RAM of Register file (accumulators or

index registers)

256 to 512 bytes of on-chip static RAM

2 or 8 Kbytes of TDSRAM (Teletext and Display

Storage RAM)

28 fully programmable I/O pins

Serial Peripheral Interface

Flexible Clock controller for OSD, Data Slicer

and Core clocks running from a single low

frequency external crystal.

Enhanced display controller with 26 rows of

40/80 characters

鈥?2 sets of 512 characters

鈥?Serial and Parallel attributes

鈥?10x10 dot matrix, definable by user

鈥?4/3 and 16/9 supported in 50/60Hz and 100/

120 Hz mode

鈥?Rounding, fringe, double width, double height,

scrolling, cursor, full background color, half-

intensity color, translucency and half-tone

modes

Teletext unit, including Data Slicer, Acquisition

Unit and up to 8 Kbytes RAM for data storage

VPS and Wide Screen Signalling slicer

Integrated Sync Extractor and Sync Controller

14-bit Voltage Synthesis for tuning reference

voltage

Up to 6 external interrupts plus one Non-

Maskable Interrupt

8 x 8-bit programmable PWM outputs with 5V

open-drain or push-pull capability

16-bit watchdog timer with 8-bit prescaler

1 or 2 16-bit standard timer(s) with 8-bit

prescaler

PSDIP56

TQFP64

See end of Datasheet for ordering information

I虜C Master/Slave (on some devices)

s

4-channel A/D converter; 5-bit guaranteed

s

Rich instruction set and 14 addressing modes

s

Versatile

development

tools,

including

Assembler, Linker, C-compiler, Archiver,

Source Level Debugger and hardware

emulators with Real-Time Operating System

available from third parties

s

Pin-compatible EPROM and OTP devices

available

Device Summary

s

Device

ST92195C3

ST92195C4

ST92195C5

ST92195C6

ST92195C7

ST92195C8

ST92195C9

ST92195D5

ST92195D6

ST92195D7

ROM

48K

56K

64K

84K

96K

48K

56K

64K

RAM TDSRAM

256

2K

6K

I虜C

Timer

512

No

8K

1

512

8K

Yes

2

October 2003

1/249

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next

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