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ST24LW21M1 Datasheet

  • ST24LW21M1

  • I2C Serial EEPROM

  • 154.35KB

  • 21頁

  • ETC

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ST24LC21B, ST24LW21
ST24FC21, ST24FW21
1 Kbit (x8) Dual Mode Serial EEPROM
for VESA PLUG & PLAY
1 MILLION ERASE/WRITE CYCLES
40 YEARS DATA RETENTION
3.6V to 5.5V SINGLE SUPPLY VOLTAGE
HARDWARE WRITE CONTROL (ST24LW21
and ST24FW21)
TTL SCHMITT-TRIGGER on VCLK INPUT
100k / 400k Hz COMPATIBILITY with the I
2
C
BUS BIT TRANSFER RANGE
TWO WIRE SERIAL INTERFACE I
2
C BUS
COMPATIBLE
I
2
C PAGE WRITE (up to 8 Bytes)
I
2
C BYTE, RANDOM and SEQUENTIAL READ
MODES
SELF TIMED PROGRAMMING CYCLE
AUTOMATIC ADDRESS INCREMENTING
ENHANCED ESD/LATCH UP
PERFORMANCES
ERROR RECOVERY MECHANISM
(ST24FC21 and ST24FW21) VESA 2
COMPATIBLE
DESCRIPTION
The ST24LC21B, ST24LW21, ST24FC21 and
ST24FW21 are 1K bit electrically erasable pro-
grammable memory (EEPROM), organized in
128x8 bits. In the text, products are referred as
ST24xy21, where "x" is either "L" for VESA 1 or "F"
for VESA 2 compatible memories and where "y"
indicates the Write Control pin connection: "C"
means WC on pin 7 and "W" means WC on pin 3.
Table 1. Signal Names
SDA
SCL
V
CC
V
SS
VCLK
WC
Serial Data Address Input/Output
Serial Clock (I
2
C mode)
Supply Voltage
Ground
Clock Transmit only mode
Write Control
Note:
WC signal is only available for ST24LW21 and ST24FW21
products.
8
1
PSDIP8 (B)
0.25mm Frame
8
1
SO8 (M)
150mil Width
Figure 1. Logic Diagram
VCC
SCL
VCLK
WC
ST24xy21
SDA
VSS
AI01741
January 1999
1/21

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