DUAL INSTRUCTION SET, JAVACARD鈩?/div>
AND NATIVE
I
4-STAGE PIPELINE
I
16 GENERAL PURPOSE 32-BIT REGISTERS,
AND SPECIAL REGISTERS
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4 MASKABLE INTERRUPT LEVELS
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SUPERVISOR AND USER MODES
SECURITY
I
CPU SECURITY INSTRUCTIONS
鈥?DES and 3DES instructions
鈥?Fast Multiply and Accumulate instructions for
Public Key and Elliptic Curve Cryptography
鈥?CRC instruction
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RANDOM NUMBER GENERATOR
I
EEPROM FLASH PROGRAMMING MODE
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CLOCK AND POWER MANAGEMENT
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VOLTAGE AND CLOCK FREQUENCY
SENSORS
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ADVANCED MEMORY PROTECTION
鈥?/div>
Memory Protection Unit
for application
firewalling and peripheral access control
鈥?Domain switching securely controlled by
protected Context Stack
鈥?Native/Java, Code/Data memory attributes
with 128-byte granularity
I
FOUR WORKING STACKS
鈥?Java stack with both 16 and 32-bit accesses
鈥?User and Supervisor mode stacks
鈥?Security Context stack
Figure 1. Delivery Form
4
4
4
Micromodule
CRYPTOGRAPHIC LIBRARY
I
ASYMMETRICAL ALGORITHMS
鈥?Software Crypto libraries in separate ROM
area for efficient algorithm coding using a set
of advanced functions. RSA, signature/
verification.
鈥?RSA key calculation including Prime number
generation SHA-1
I
SYMMETRICAL ALGORITHMS
鈥?DES, Triple DES, AES
CRYPTOGRAPHY PERFORMANCE
The following table provides the cryptographic
performances of the ST22N256 based on ST
Crypto Library.
Table 1. Preliminary Cryptographic
Performances
Algorithm
RSA
1024 bits
RSA
2048 bits
DES
SHA-1
AES-128
1.
2.
Internal clock at 33 MHz
CRT: Chinese Reminder Theorem
4
Wafer
Function
Signature with CRT
Signature without CRT
(2)
Verification (e=0x10001)
Signature with CRT
Signature without CRT
Verification (e=0x10001)
Triple
Single
512-bit Block
Encryption including subkey
computation
Time
(1)
79.0 ms
242.0 ms
3.6 ms
485.0 ms
1.7 s
11.0 ms
18 碌s
8 碌s
194 碌s
85 碌s
June 2004
For further information contact your local ST sales office.
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