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ST2202 Datasheet

  • ST2202

  • 8 BIT Integrated Microcontroller with 256K Bytes ROM

  • 1940.00KB

  • 65頁

  • ETC

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ST
Sitronix
PRELIMINARY
Notice: This is not a final specification. Some parameters are subject to change.
ST2202
8 BIT Integrated Microcontroller with 256K Bytes ROM
1. FEATURES
Totally static 8-bit CPU
ROM: 256K x 8-bit
RAM: 4K x 8-bit
Stack: Up to 128-level deep
Operation voltage: 2.4V ~ 5.5V
Operation frequency:
鈥?3.0Mhz@2.4V(Min.)
鈥?4.0Mhz@2.7V(Min.)
Low Voltage Detector (LVD)
Memory interface to ROM, RAM, Flash
Memory configuration
鈥?Three kinds of bank for program, data and interrupts
鈥?12-bit bank register supports up to 44M bytes
鈥?6 programmable chip-selects with 4 modes
鈥?Maximum single device of 16M bytes at
CS5
General-Purpose I/O (GPIO) ports
鈥?48 multiplexed CMOS bidirectional bit programmable
I/Os
鈥?Hardware de-bounce option for Port-A
鈥?Bit programmable pull-up for input pins
鈥?Bit programmable pull-up/down and open-drain/CMOS
for Port-C
Programmable Watchdog Timer (WDT)
Timer/Counter
鈥?Two 8-bit timer, one can be a 16-bit event counter
鈥?One 8-bit Base timer with 5 coexistent interrupt time
settings
Three clocking outputs
鈥?Clock sources including Timer0/1, baud rate generator
11 prioritized interrupts with dedicated exception
vectors
鈥?External interrupt (edge triggered)
鈥?TIMER0 interrupt
鈥?TIMER1 interrupt
鈥?BASE timer interrupt
鈥?PORTA interrupt (transition triggered)
鈥?DAC reload interrupt
鈥?LCD frame interrupt
鈥?SPI interrupts (x2)
鈥?UART interrupts (x2)
Dual clock sources with warm-up timer
鈥?Low frequency crystal oscillator (OSCX)
路路路路路路路路路路路路路路路路路路路路路路路路路路路路路路路路路路路路路路路路路路路路路路路路路路路路32768 Hz
鈥?RC oscillator (OSC) 路路路路路路路路路路路路路路路路路路路路路路路路路路路路路路路 500K ~ 4M Hz
鈥?High frequency crystal/resonator oscillator
(Bonding option)路路路路路路 455K~4M Hz
Ver 2.0a
1
/
65
Direct Memory Access (DMA)
鈥?Block-to-Block transfer
鈥?Block to Single port
LCD Controller (LCDC)
鈥?Software programmable screen size up to 240X120
(including 160x160, 160x80, etc.)
鈥?Support 1-, 4-bit LCD data bus
鈥?Share system memory with display memory
鈥?Unique internal bus for memory sharing with no loss of
the CPU time
鈥?Diverse functions including virtual screen , panning ,
scrolling , contrast control and alternating signal
generator
鈥?Support software 16 gray levels
Universal Asynchronous Receiver/Transmitter (UART)
鈥?Full-duplex operation
鈥?Baud rate generator with one digital PLL
鈥?Standard baud rates of 600 bps to 115.2 kbps
鈥?Direct glueless support of IrDA physical layer protocol
鈥?Two sets of I/Os (TX,RX) for two independent devices
Serial Peripheral Interface (SPI)
鈥?Master and slave modes
鈥?5 serial signals including enable and data-ready
鈥?One stage buffer for transmitter and receiver for
continuous data exchange
鈥?Programmable data length from 7-bit to 16-bit
Programmable Sound Generator (PSG)
鈥?Two channels with three playing modes
鈥?Tone/noise generator
鈥?16-level volume control
鈥?8-bit PWM DAC for speech/voice
鈥?Two dedicated outputs for directly driving and large
current
Three power down modes
鈥?WAI0 mode
鈥?WAI1 mode
鈥?STP mode
2003-May-05

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