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t
PHL
Power-down protection on inputs and outputs
26惟 series resistor on A-side outputs
Operating voltage range:
鈥?V
CCA
(Opr) = 1.2V to 3.6V
鈥?V
CCB
(Opr) = 1.2V to V
CCA
Latch-up performance exceeds 100mA per
JESD 78, Class II
ESD performance exceeds JESD22
鈥?2000-V Human-body model (A114-A)
DFN6L
Description
The ST1G3236 is a dual supply low voltage
CMOS 1-bit bus Transceiver fabricated with sub-
micron silicon gate and five-layer metal wiring
C2MOS technology. Designed for use as an
interface between a 3.3V bus and a 2.5V or 1.2V
bus in mixed supply systems of 3.3V/1.2V,
3.3V/2.5V and 2.5V/1.8V, the ST1G3236 achieves
high speed operation while maintaining low power
dissipation. V
CCA
and V
CCB
can be powered from
1.2V to 3.6V respectively. The DIR pin is designed
to track V
CCB
.
The device is intended for two-way asynchronous
communication between data buses and the
direction of data transmission is determined by
DIR inputs.
All inputs are equipped with protection circuits
against static discharge, giving them 2kV ESD
immunity and transient excess voltage.
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Table 1.
Device summary
Order code
ST1G3236DTR
Package
DFN6L (1.2x1mm)
Packaging
Tape and Reel
July 2007
Rev 1
1/19
www.st.com
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