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ST16654 Datasheet

  • ST16654

  • QUAD UART WITH 64-BYTE FIFO AND INFRARED (IrDA) ENCODER/DECO...

  • 49頁

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ST16C654/654D
QUAD UART WITH 64-BYTE FIFO AND
INFRARED (IrDA) ENCODER/DECODER
DESCRIPTION
The ST16C654
*
1
is a universal asynchronous receiver and transmitter (UART) with a dual foot print interface
compatible with the ST16C554 and ST68C554. The 654 is an enhanced UART with 64 byte FIFOs, automatic
hardware/software flow control, and data rates up to 1.5Mbps. Onboard status registers provide the user with error
indications and operational status, modem interface control. System interrupts may be tailored to meet user
requirements. An internal loopback capability allows onboard diagnostics. The 654 is available in 64 pin TQFP,
68 pin PLCC, and 100 pin QFP packages. The 64 pin package offers the 16 interface mode which is compatible
with the industry standard ST16C554. The 68 and 100 pin packages offer an additional 68 mode which allows easy
integration with Motorola, and other popular microprocessors. The ST16C654CQ64 (64 pin) offers three state
interrupt control while the ST16C654DCQ64 provides constant active interrupt outputs. The 64 pin devices do
not offer TXRDY/RXRDY outputs or the default clock select option (CLKSEL). The 100 pin packages offer faster
channel status access by providing separate outputs for TXRDY and RXRDY, offer separate Infrared TX outputs
and a musical instrument clock input (MIDICLK). The 654 combines the package interface modes of the 16C454/
554 and 68/C454/554 series on a single integrated chip.
FEATURES
路
Compatibility with the Industry Standard
ST16C454/554, ST68C454/554, TL16C554
路
1.5 Mbps transmit/receive operation (24MHz)
路
64 byte transmit FIFO
路
64 byte receive FIFO with error flags
路
Automatic software/hardware flow control
路
Programmable Xon/Xoff characters
路
Independent transmit and receive control
路
Software selectable Baud Rate Generator pre-
scaleable clock rates of 1X, 4X.
路
Four selectable Transmit/Receive FIFO interrupt
trigger levels
路
Standard modem interface or infrared IrDA en-
coder/decoder interface
路
Software flow control turned off optionally by any
(Xon) RX character
路
Independent MIDI interface on 100 pin packages
路
100 pin packages offer internal register FIFO
monitoring and separate IrDA TX outputs
路
Sleep mode ( 200mA stand-by)
PLCC Package
INTSEL
-CDD
63
60
59
58
57
56
55
54
53
-CDA
GND
VCC
RXD
63
-RID
62
RXA
-RIA
D7
D6
D5
D4
D3
D2
D1
67
68
66
D0
65
-DSRA
-CTSA
-DTRA
VCC
-RTSA
INTA
-CSA
TXA
-IOW
TXB
-CSB
INTB
-RTSB
GND
-DTRB
-CTSB
-DSRB
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
64
9
8
7
6
5
4
3
2
1
-DSRD
-CTSD
-DTRD
GND
-RTSD
INTD
-CSD
TXD
-IOR
TXC
-CSC
INTC
-RTSC
VCC
-DTRC
-CTSC
-DSRC
ST16C654CJ68
16 MODE
52
51
50
49
48
47
46
45
44
16/-68
-RXRDY
-TXRDY
GND
RXC
XTAL1
XTAL2
CLKSEL
RESET
-CDB
-RIC
-RIB
RXB
A2
A1
A0
ORDERING INFORMATION
Part number
Pins
Package Operating temperature
Part number
Pins
Package Operating temperature
ST16C654CJ68
ST16C654CQ64
ST16C654DCQ64
ST16C654CQ100
68
64
64
100
PLCC
TQFP
TQFP
QFP
0擄 C to + 70擄 C
0擄 C to + 70擄 C
0擄 C to + 70擄 C
0擄 C to + 70擄 C
ST16C654IJ68
68
PLCC
ST16C654IQ64
64
TQFP
ST16C654DIQ64 64
TQFP
ST16C654IQ100
100 QFP
Note *1: Patent Pending
-40擄 C to + 85擄 C
-40擄 C to + 85擄 C
-40擄 C to + 85擄 C
-40擄 C to + 85擄 C
Rev. 4.10
5-65
-CDC

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