ST1305
High Endurance CMOS 192 bit EEPROM
With Secure Logic Access Control
BRIEF DATA
s
s
s
Single 5 V Supply Voltage
Programming Time: 5 ms
Memory Divided Into:
鈥?16 bits of Circuit Identification
鈥?48 bits of Card Identification
鈥?48 bits of Count Data
鈥?16 bits of Certificate
鈥?48 bits of Transport Code
鈥?64 bits of Issuer Data
Figure 1. Delivery Forms
s
s
Counting Capability up to 262,144 Units
Circuit Protected by Transport Code for Delivery
from ST to the Customer
5 External Contacts Only (ISO 7816 Compatible)
Answer to Reset (Fully Compatible with ISO 7816-3)
E.S.D. Protection Greater Than 4000 V
Power-On and Low V
CC
Reset
10 Years Data Retention
1 Million Erase/Write Cycles Endurance
Micromodule
Wafer
s
s
s
s
s
s
Figure 2. Pin Connection
VCC
RST
ST1305
CLK
I/O
DESCRIPTION
The ST1305 is a 192-bit EEPROM device with associat-
ed security logic to control memory access. The circuit
includes counting capabilities and thus is very well
adapted to prepaid card applications.
The ST1305 is protected by hard-wired security logic
GND
and special fuses. The memory is arranged as a matrix
of 24x8 cells, accessed in a serial bit-wise fashion for
reading and programming, and in a byte-wise fashion
Table 1. Signal Names
for internal erasing.
CLK
Clock
The device recognises three commands issued via the
RST and CLK pins (as described in the full data sheet):
鈥?RESET: to reset the internal address register to 00d
鈥?READ: to increment the internal address register,
and read the data bit at that address
鈥?PROG: to program the bit at the current address.
RST
I/O
V
CC
GND
Reset
Serial Data Input/Output
Supply Voltage
Ground
AI01032
BD.05/9803V1
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STMICROELECTRONICS
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