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ST10R272L-B0
16-BIT ROMLESS LOW VOLTAGE MCU WITH MAC
ERRATA SHEET
1 INTRODUCTION
This errata sheet describes the functional and electrical problems known in the step B0 of the
ST10R272L-B0. This is the erratasheet of the ST10R272L datasheet version 1.3 of March
2001.
2 FUNCTIONAL PROBLEMS
The following malfunctions are known in this step:
2.1 ST_PWRDN.1: EXECUTION OF PWRDN INSTRUCTION WHILE NMI PIN IS HIGH
When PWRDN instruction is executed while NMI pin is at a high level, power-down mode
should not be entered, and the PWRDN instruction should be ignored. However, under the
conditions described below, the PWRDN instruction may not be ignored, and no further in-
structions are fetched from external memory, i.e. the CPU is in a quasi-idle state. This prob-
lem will only occur in the following situations:
1) the instructions following the PWRDN instruction are located in an external memory, and
a multiplexed bus configuration with memory tristate waitstate (bit MTTCx= 0) is used,
2) the instruction preceding the PWRDN instruction writes to external memory or an XPeriph-
eral (XRAM, CAN), and the instructions following the PWRDN instruction are located in ex-
ternal memory. In this case, the problem will occur for any bus configuration.
Note:
the on-chip peripherals still work correctly: if the Watchdog Timer is not disabled, it will
reset the device upon an overflow. Interrupts and PEC transfers, however, can not be proc-
essed. If NMI is asserted low while the device is in this quasi-idle state, power-down mode is
entered.
No problem will occur if the NMI pin is low: the chip will normally enter power-down mode.
Workaround:
Ensure that no instruction which writes to external memory or an XPeripheral
precedes the PWRDN instruction, otherwise insert e.g. a NOP instruction in front of PWRDN.
When a multiplexed bus with memory tristate waitstate is used, the PWRDN instruction
should be executed from internal RAM or XRAM.
Rev. 1.1
March 2001
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