ST10F163
16-BIT MCU WITH 128KBYTE FLASH MEMORY
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PEC
Interrupt Controller
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P.4 P.1 P.0
PLL
GPT1&2
EBC
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SSP
BRG
BRG
ASC
P.6
P.5
P.3
P.2
April 1999
This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Watchdog
1/58
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HIGH PERFORMANCE CPU
鈥?HIGH PERFORMANCE 16-BIT CPU WITH
4-STAGE PIPELINE
鈥?80ns INSTRUCTION CYCLE TIME @ 25MHz CPU
CLOCK
鈥?400ns MULTIPLICATION (16
脳
16 BITS)
鈥?800ns DIVISION (32 / 16 BIT)
鈥?ENHANCED BOOLEAN BIT MANIPULATION FA-
CILITIES
鈥?ADDITIONAL INSTRUCTIONS TO SUPPORT HLL
AND OPERATING SYSTEMS
鈥?SINGLE-CYCLE CONTEXT SWITCHING SUP-
PORT
MEMORY ORGANIZATION
鈥?UP TO 16 MBYTES LINEAR ADDRESS SPACE
FOR CODE AND DATA (1MBYTE WITH SSP
USED)
鈥?1 KBYTES ON-CHIP RAM
鈥?128 KBYTES ON-CHIP FLASH MEMORY
鈥?4 INDEPENDENTLY ERASABLE BANKS OF
FLASH
FAST AND FLEXIBLE BUS
鈥?PROGRAMMABLE EBC
鈥?8-BIT OR 16-BIT EXTERNAL DATA BUS
鈥?MULTIPLEXED OR DEMULTIPLEXED EXTER-
NAL ADDRESS/DATA BUSES
鈥?FIVE PROGRAMMABLE CHIP-SELECT SIGNALS
鈥?HOLD AND HOLD-ACKNOWLEDGE BUS ARBI-
TRATION SUPPORT
ON-CHIP BOOTSTRAP LOADER
FAIL-SAFE PROTECTION
鈥?PROGRAMMABLE WATCHDOG TIMER
鈥?OSCILLATOR WATCHDOG
INTERRUPT
鈥?8-CHANNEL INTERRUPT-DRIVEN SINGLE-CY-
CLE DATA TRANSFER FACILITIES VIA PERIPH-
ERAL EVENT CONTROLLER (PEC)
鈥?16-PRIORITY-LEVEL INTERRUPT SYSTEM
WITH 20 SOURCES, SAMPLE-RATE DOWN TO
40ns
TIMERS
鈥?TWO GENERAL PURPOSE TIMER UNITS WITH 5
TIMERS
CLOCK GENERATION
鈥?ON-CHIP PLL
鈥?DIRECT OR PRESCALED CLOCK INPUT
PQFP100 (14 x 14 mm)
(Plastic Quad Flat Pack)
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UP TO 77 GENERAL PURPOSE I/O LINES
IDLE AND POWER DOWN MODES
SERIAL CHANNELS
鈥?SYNCHRONOUS/ASYNCHRONOUS
鈥?HIGH-SPEEDSYNCHRONOUS SERIAL PORTSSP
DEVELOPMENT SUPPORT
鈥?C-COMPILERS, MACRO-ASSEMBLER PACKAG-
ES, EMULATORS, EVALUATION BOARDS,
HLL-DEBUGGERS, SIMULATORS, LOGIC ANA-
LYZER DISASSEMBLERS, PROGRAMMING
BOARDS
PACKAGE
鈥?100-PIN THIN QUAD FLAT PACK (TQFP)
FLASH
CPU
RAM