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SST34HF324G Datasheet

  • SST34HF324G

  • 32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory

  • 30頁

  • SST   SST

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32 Mbit Dual-Bank Flash + 4 Mbit SRAM ComboMemory
SST34HF324G
SST34HF324G32Mb Dual-Bank Flash + 4 Mb SRAM MCP ComboMemory
Data Sheet
FEATURES:
鈥?Flash Organization: 2M x16
鈥?32 Mbit: 24Mbit + 8Mbit
鈥?Concurrent Operation
鈥?Read from or Write to SRAM while
Erase/Program Flash
鈥?SRAM Organization:
鈥?4 Mbit: 256K x16
鈥?Single 2.7-3.3V Read and Write Operations
鈥?Superior Reliability
鈥?Endurance: 100,000 Cycles (typical)
鈥?Greater than 100 years Data Retention
鈥?Low Power Consumption: (typical values @ 5 MHz)
鈥?Active Current: Flash 10 mA (typical)
SRAM 6 mA (typical)
鈥?Standby Current: 10 碌A(chǔ) (typical)
鈥?Hardware Sector Protection (WP#)
鈥?Protects 4 outer most sectors (8 KWord) in the
smaller bank by holding WP# low and unprotects
by holding WP# high
鈥?Hardware Reset Pin (RST#)
鈥?Resets the internal state machine to reading
data array
鈥?Sector-Erase Capability
鈥?Uniform 2 KWord sectors
鈥?Block-Erase Capability
鈥?Uniform 32 KWord blocks
鈥?Read Access Time
鈥?Flash: 70 ns
鈥?SRAM: 70 ns
鈥?Erase-Suspend / Erase-Resume Capabilities
鈥?Latched Address and Data
鈥?Fast Erase and Word-Program (typical):
鈥?Sector-Erase Time: 18 ms
鈥?Block-Erase Time: 18 ms
鈥?Chip-Erase Time: 35 ms
鈥?Program Time: 7 碌s
鈥?Automatic Write Timing
鈥?Internal
V
PP
Generation
鈥?End-of-Write Detection
鈥?Toggle Bit
鈥?Data# Polling
鈥?CMOS I/O Compatibility
鈥?JEDEC Standard Command Set
鈥?Packages Available
鈥?48-ball LFBGA (6mm x 8mm)
鈥?All non-Pb (lead-free) devices are RoHS compliant
PRODUCT DESCRIPTION
The SST34HF324G ComboMemory devices integrate a
2M x16 CMOS flash memory bank with 256K x16 CMOS
SRAM memory bank in a multi-chip package (MCP).
These devices are fabricated using SST鈥檚 proprietary, high-
performance CMOS SuperFlash technology incorporating
the split-gate cell design and thick-oxide tunneling injector
to attain better reliability and manufacturability compared
with alternate approaches. The SST34HF324G devices
are ideal for applications such as cellular phones, GPS
devices, PDAs, and other portable electronic devices in a
low power and small form factor system.
The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore, the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase
and Program times increase with accumulated Erase/Pro-
gram cycles. The SST34HF324G devices offer a guaran-
teed endurance of 10,000 cycles. Data retention is rated at
greater than 100 years. With high-performance Program
operations, the flash memory banks provide a typical Pro-
漏2006 Silicon Storage Technology, Inc.
S71310-00-000
6/06
1
gram time of 7 碌sec. The entire flash memory bank can be
erased and programmed word-by-word in 4 seconds (typi-
cally) for the SST34HF324G, when using interface features
such as Toggle Bit or Data# Polling to indicate the comple-
tion of Program operation. To protect against inadvertent
flash write, the SST34HF324G devices contain on-chip
hardware and software data protection schemes.
The flash and SRAM operate as two independent memory
banks with respective bank enable signals. The memory
bank selection is done by two bank enable signals. The
SRAM bank enable signal, BES#, selects the SRAM bank.
The flash memory bank enable signal, BEF#, has to be
used with Software Data Protection (SDP) command
sequence when controlling the Erase and Program opera-
tions in the flash memory bank. The memory banks are
superimposed in the same memory address space where
they share common address lines, data lines, WE# and
OE# which minimize power consumption and area. See
Table 3 for memory organization.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
ComboMemory is a trademark of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.

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