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SST29EE010-120-4CPH Datasheet

  • SST29EE010-120-4CPH

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1 Megabit (128K x8) Page-Mode EEPROM
SST29EE010 / SST29LE010 / SST29VE010
Data Sheet
FEATURES:
鈥?Single Voltage Read and Write Operations
鈥?5.0V-only for the SST29EE010
鈥?3.0-3.6V for the SST29LE010
鈥?2.7-3.6V for the SST29VE010
鈥?Superior Reliability
鈥?Endurance: 100,000 Cycles (typical)
鈥?Greater than 100 years Data Retention
鈥?Low Power Consumption
鈥?Active Current: 20 mA (typical) for 5V and
10 mA (typical) for 3.0/2.7V
鈥?Standby Current: 10 碌A(chǔ) (typical)
鈥?Fast Page-Write Operation
鈥?128 Bytes per Page, 1024 Pages
鈥?Page-Write Cycle: 5 ms (typical)
鈥?Complete Memory Rewrite: 5 sec (typical)
鈥?Effective Byte-Write Cycle Time: 39 碌s
(typical)
鈥?Fast Read Access Time
鈥?5.0V-only operation: 90 and 120 ns
鈥?3.0-3.6V operation: 150 and 200 ns
鈥?2.7-3.6V operation: 200 and 250 ns
鈥?Latched Address and Data
鈥?Automatic Write Timing
鈥?Internal V
PP
Generation
鈥?End of Write Detection
鈥?Toggle Bit
鈥?Data# Polling
鈥?Hardware and Software Data Protection
鈥?TTL I/O Compatibility
鈥?JEDEC Standard
鈥?Flash EEPROM Pinouts and command sets
鈥?Packages Available
鈥?32 Pin PDIP
鈥?32-Pin PLCC
鈥?32-Pin TSOP (8mm x 14mm, 8mm x 20mm)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PRODUCT DESCRIPTION
The SST29EE010/29LE010/29VE010 are 128K x8
CMOS Page-Write EEPROMs manufactured with SST鈥檚
proprietary, high performance CMOS SuperFlash tech-
nology. The split-gate cell design and thick oxide tunnel-
ing injector attain better reliability and manufacturability
compared with alternate approaches. The
SST29EE010/29LE010/29VE010 write with a single
power supply. Internal Erase/Program is transparent to
the user. The SST29EE010/29LE010/29VE010
conform to JEDEC standard pinouts for byte-wide
memories.
Featuring high performance Page-Write, the
SST29EE010/29LE010/29VE010 provide a typical Byte-
Write time of 39 碌sec. The entire memory, i.e., 128
KBytes, can be written page-by-page in as little as 5
seconds, when using interface features such as Toggle
Bit or Data# Polling to indicate the completion of a Write
cycle. To protect against inadvertent write, the
SST29EE010/29LE010/29VE010 have on-chip hard-
ware and Software Data Protection schemes. Designed,
manufactured, and tested for a wide spectrum of applica-
tions, the SST29EE010/29LE010/29VE010 are offered
with a guaranteed Page-Write endurance of 10
4
cycles.
Data retention is rated at greater than 100 years.
The SST29EE010/29LE010/29VE010 are suited for ap-
plications that require convenient and economical updat-
ing of program, configuration, or data memory. For all
system applications, the SST29EE010/29LE010/
29VE010 significantly improve performance and reliabil-
ity, while lowering power consumption. The
SST29EE010/29LE010/29VE010 improve flexibility
while lowering the cost for program, data, and configura-
tion storage applications.
To meet high density, surface mount requirements, the
SST29EE010/29LE010/29VE010 are offered in 32-pin
TSOP and 32-lead PLCC packages. A 600-mil, 32-pin
PDIP package is also available. See Figures 1 and 2 for
pinouts.
Device Operation
The SST Page-Mode EEPROM offers in-circuit electrical
write capability. The SST29EE010/29LE010/29VE010
does not require separate Erase and Program opera-
tions. The internally timed write cycle executes both
erase and program transparently to the user. The
SST29EE010/29LE010/29VE010 have industry stan-
dard optional Software Data Protection, which SST
recommends always to be enabled. The SST29EE010/
29LE010/29VE010 are compatible with industry stan-
dard EEPROM pinouts and functionality.
Read
The Read operations of the SST29EE010/29LE010/
29VE010 are controlled by CE# and OE#, both have to
be low for the system to obtain data from the outputs.
CE# is used for device selection. When CE# is high, the
SSF is a trademark of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
漏 2000 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
304-4 11/00
S71061
1

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