SSM1105V
Scalar System Memory (SSM)
for Image Processor ICs
NOT FOR NEW DESIGN
FEATURES SUMMARY
s
System solution for use with image processing
scalar ICs
鈥?For LCD monitors, projectors, and TVs
鈥?Compatible with Pixelworks PW11x/PWx64
families (and similar image processors or mi-
cro-controllers)
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decoders, chip-selects, inverters; and to
prioritize interrupts from DDC, I
2
C, PWM
Figure 1. Packages
Single integrated package, including:
鈥?Dual bank Flash memories
鈥?DDC, I
2
C, and PWM channels
鈥?General purpose I/O
鈥?Programmable logic
鈥?In-System Programming via JTAG
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Dual bank Flash memories
鈥?Provide concurrent operation
鈥?5 Mbit main Flash memory
鈥?384 Kbit secondary Flash memory (divided
into 10 small sectors)
鈥?Programmable Decode PLD for flexible ad-
dress mapping of both memories
TQFP100 (U)
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Dual Display Data Channels (DDC)
鈥?Supports DDC for both analog RGB and digi-
tal DVI video input channels
鈥?DDC1/DDC2B VESA standard compliant
鈥?256 byte SRAM buffer for each DDC channel
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In-System Programming (ISP) with JTAG
鈥?Program entire chip in 30-40 seconds with no
involvement of the processor
鈥?Program with low-cost FlashLINK
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Dual independent I
2
C channels
鈥?Each capable of master or slave operation
鈥?Control A/D converters, video decoders, and
future devices (tuner, audio, etc.)
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Content Security: Programmable Security Bit
blocks access of device programmers / readers
Zero-Power Technology: memory and PLD
blocks automatically switch to stand-by current
between input changes
Package and Specifications
鈥?100-pin TQFP, 14 x 14mm
鈥?90 ns memory access time
鈥?V
CC
Operating Voltage: 2.7V to 3.6V
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Four Pulse Width Modulator (PWM) channels
鈥?16-bit resolution for period and for duty cycle
鈥?16-bit clock prescalers
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Seven I/O ports with 52 I/O pins for Multifunction
I/O: GPIO, DDC, I
2
C, PWM, PLD I/O, and JTAG
3000 gate PLD with 16 macrocells, for creating
glue logic, state machines, clock dividers,
s
s
November 2002
This is information on a product still in production but not recommended for new designs.
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