PF805-04
SRM20V100LLMX
7
SRM20V100LLMX
7
1M-Bit Static RAM
ge
lta
Vo n
w ratio s
Lo pe ct
O odu
Pr
s
DESCRIPTION
q
Low Supply Voltage
q
Wide Temperature Range
q
Low Supply Current
q
Access Time 70ns (2.7V)
q
131,072 Words脳8-Bit Asynchronous
The SRM20V100LLMX
7
is an 131,072 words脳8-bit asynchronous, static, random access memory on a monolithic
CMOS chip. Its very low standby power requirement makes it ideal for applications requiring non-volatile storage
with back-up batteries. And 鈥?5 to 85擄C operating temperature range makes it ideal for portable equipment.
The asynchronous and static nature of the memory requires no external clock or refreshing circuit. Both the
input and output ports are TTL compatible and 3-state output allows easy expansion of memory capacity.
s
FEATURES
q
Wide temperature range ..... 鈥?5 to 85擄C
q
Fast Access time ................. SRM20V100LLMX
7
70ns (Max.)
q
Low supply current .............. standby: 0.6碌A(chǔ) (Typ.): LL Version
0.3碌A(chǔ) (Typ.): SL Version
operation: 8mA/1MHz (Typ.)
q
Completely static ................. No clock required
q
Supply voltage..................... 2.7V to 3.6V
q
TTL compatible inputs and outputs
q
3-state output with wired-OR capability
q
Non-volatile storage with back-up batteries
SOP6-32pin (plastic)
q
Package ...... SRM20V100LLMX
7
SRM20V100LLTX
7
TSOP (
I
)-32pin (plastic)
SRM20V100LLRX
7
TSOP (
I
)-32pin-R1 (plastic)
SRM20V100LLKX
7
Slim-TSOP (
I
)-32pin (plastic)
SRM20V100LLYX
7
Slim-TSOP (
I
)-32pin-R1 (plastic)
s
PIN CONFIGURATION
(SOP6)
N.C.
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/01
I/02
I/03
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
DD
A15
CS2
WE
A13
A8
A9
A11
OE
A10
CS1
I/08
I/07
I/06
I/05
I/04
SRM20V100LLMT
(TSOP/Slim-TSOP)
A11
A9
A8
A13
WE
CS2
A15
V
DD
N.C.
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CS1
I/08
I/07
I/06
I/05
I/04
V
SS
I/03
I/02
I/01
A0
A1
A2
A3
SRM20V100LLTX/KX
s
BLOCK DIAGRAM
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
CS1
CS2
10
X Decoder
(TSOP-R1/Slim-TSOP-R1)
1024
Memory Cell Array
1024脳128脳8
128脳8
7
128
Column Gate
A4
A5
A6
A7
A12
A14
A16
N.C.
V
DD
A15
CS2
WE
A13
A8
A9
A11
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
SRM20V100LLRX/YX
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
A3
A2
A1
A0
I/01
I/02
I/03
V
SS
I/04
I/05
I/06
I/07
I/08
CS1
A10
OE
Address Buffer
Y
Decoder
CS1, CS2
Chip
Control
8
隆PIN
DESCRIPTION
A0 to A16 Address Input
WE
Write Enable
OE
Output Enable
CS1, CS2 Chip Select
I/O1 to I/O8 Data I/O
V
DD
Power Supply (2.7V to 3.6V)
V
SS
Power Supply (0V)
N. C.
No connection
OE
WE
OE, WE
Chip
Control
I/O Buffer
I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8
1
1
2
3
4
5
6
7
8
