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SPT7850 Datasheet

  • SPT7850

  • 10-BIT, 20 MSPS, 140 mW A/D CONVERTER

  • 13頁

  • FAIRCHILD

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SPT7850
10-BIT, 20 MSPS, 140 mW A/D CONVERTER
TECHNICAL DATA
JUNE 15, 2001
FEATURES
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Monolithic 20 MSPS converter
140 mW power dissipation
On-chip track-and-hold
Single +5 V power supply
TTL/CMOS outputs
5 pF input capacitance
Low cost
Tri-state output buffers
High ESD protection: 3,500 V minimum
Selectable +3 V or +5 V logic I/O
APPLICATIONS
鈥?All high-speed applications where low power
dissipation is required
鈥?Video imaging
鈥?Medical imaging
鈥?IR imaging
鈥?Scanners
鈥?Digital communications
GENERAL DESCRIPTION
The SPT7850 is a 10-bit monolithic, low-cost, ultralow-
power analog-to-digital converter capable of minimum
word rates of 20 MSPS. The on-chip track-and-hold func-
tion assures very good dynamic performance without the
need for external components. The input drive require-
ments are minimized due to the SPT7850鈥檚 low input
capacitance of only 5 pF.
Power dissipation is extremely low at only 140 mW typical
(165 mW maximum) at 20 MSPS with a power supply of
+5.0 V. The digital outputs are +3 V or +5 V, and are user
selectable. The SPT7850 is pin-compatible with an entire
family of 10-bit, CMOS converters (SPT7835/40/50/55/60/
61), which simplifies upgrades. The SPT7850 has incorpo-
rated proprietary circuit design* and CMOS processing
technologies to achieve its advanced performance. Inputs
and outputs are TTL/CMOS-compatible to interface with
TTL/CMOS logic systems. Output data format is straight
binary.
The SPT7850 is available in 28-lead 300 mil PDIP and
32-lead small (7 mm square) TQFP packages over the
commercial temperature range, and in a 28-lead SOIC
package over the industrial temperature range.
*Patent pending
BLOCK DIAGRAM
ADC Section 1
A
IN
1:8
Mux
T/H
Auto-
Zero
CMP
11-Bit
SAR
11
11
D10 Overrange
D9 (MSB)
D8
D7
D6
D5
D4
D3
D2
D1
P1
DAC
CLK In
Timing
and
Control
Enable
.
.
.
P7
P2
P8
.
.
.
ADC Section 7
ADC Section 2
ADC Section 8
T/H
Auto-
Zero
CMP
.
.
.
11-Bit
SAR
11
DAC
11
.
.
.
11
11
11-Bit
8:1
Mux/
Error
Correction
Data
Valid
Ref
In
Reference Ladder
D0 (LSB)
V
REF

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