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SP8858 Datasheet

  • SP8858

  • 1·5GHz Professional Synthesiser

  • 542.43KB

  • Zarlink   Zarlink

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SP8858
1路5GHz Professional Synthesiser
Supersedes March 1997 version, DS3843 - 3.0
DS3843 - 4.1 July 1998
LOCK DETECT
FEATURES
s
Low Residual Phase Noise (see Reference 1)
s
Operation to 1路5GHz over Full Temperature Range
s
High Input Sensitivity
s
Improved Linear Digital Phase Detector
s
Programmable Charge Pump Current: 10碌A(chǔ) to 2 mA
s
On-chip
416/17
or
48/9
Dual Modulus Prescaler
s
Three-wire Serial Data Interface
s
13-bit Reference Counter
s
15-bit M Counter
s
Stores an Alternative Programming Word
s
Facility to Program A counter Only
s
Power Saving Standby Mode
ABSOLUTE MAXIMUM RATINGS
Supply voltage
Storage temperature
Operating temperature
Prescaler input voltage
20路3V
to
17V
265擄C
to
1150擄C
255擄C
to
1125擄C
2路5V p-p
4
3
2
1
28
27 26
25
24
23
F
REF
*
POWER DOWN
V
EE
4
V
CC
4
V
CC
1
RF INPUT
RF INPUT
5
6
7
8
9
10
11
12
13
14
15
16
17 18
CP REF
F
PD
*
V
EE
3
The SP8858 is a single chip synthesiser intended for PLL
signal synthesis applications up to 1.5GHz and includes a
dual modulus prescaler (4N/N11), programmable A, M and
R dividers, digital phase detector, charge pump and lock
detect circuits.
The SP8858 is a development of the SP8853 synthesiser
with low residual phase noise, increased dynamic range
above 1GHz and an improved high gain phase detector
design that eliminates the dead-band.
The low prescaler modulus, programmable to either 16/17
or 8/9, together with the 15-bit M counter and 13-bit reference
counter make this device ideal for a diverse range of high
performance applications.
The nominal phase detector gain is set by a reference
current into pin 24 and the gain can be varied over a 4:1 range
when the device is programmed. The dividers, the phase
detector sense, the prescaler modulus and the data buffer
control logic are also programmable using the three wire
serial interface. An alternative 22-bit control word for the A
and M dividers and phase detector gain can be stored so
allowing fast frequency hopping and bandwidth switching by
simply toggling the logic level on pin 13 (F1/F2). In addition,
the A counter of the 鈥榓ctive鈥?buffer can be programmed with
only 6 bits, allowing fast hopping to adjacent channels.
A simple exclusive - or lock detect circuit is also provided,
the sensitivity of which is determined by an external capacitor.
LOCK DETECT
4
3
2
1
28
27 26
25
24
23
F
REF
*
POWER DOWN
V
EE
4
V
CC
4
V
CC
1
RF INPUT
RF INPUT
CP REF
F
PD
*
V
EE
3
NC
NC
CD
5
6
7
8
9
10
11
12
13
14
15
16
17 18
CP OUTPUT
RPD
V
CC
3
GROUND
XTAL 1
XTAL2
V
EE
2
SP8858
22
21
20
19
DATA
CLOCK
ENABLE
F1/F2
V
EE
1
NC
V
CC
2
HC28
NC
NC
CD
CP OUTPUT
RPD
V
CC
3
GROUND
XTAL 1
XTAL2
V
EE
2
SP8858
22
21
20
19
DATA
CLOCK
ENABLE
F1/F2
V
EE
1
NC
V
CC
2
HP28
Fig. 1 Pin connections (top view)
ORDERING INFORMATION
SP8858 IG HCAR
240擄C
to
185擄C
(Industrial grade)
SP8858 MG HCAR
255擄C
to
1125擄C
(Military grade)
SP8858 IG HPAS
240擄C
to
185擄C
(Industrial grade)

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