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SN65LV1224B Datasheet

  • SN65LV1224B

  • 1:10 LVDS 串行器/解串器接收器 100 - 660 Mbps

  • 26頁(yè)

  • TI

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SN65LV1023A
SN65LV1224B
www.ti.com
SLLS621C 鈥?SEPTEMBER 2004 鈥?REVISED FEBRUARY 2006
10-MHz To 66-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER
FEATURES
鈥?/div>
100-Mbps to 660-Mbps Serial LVDS Data
Payload Bandwidth at 10-MHz to 66-MHz
System Clock
Pin-Compatible Superset of
DS92LV1023/DS92LV1224
Chipset (Serializer/Deserializer) Power
Consumption <450 mW (Typ) at 66 MHz
Synchronization Mode for Faster Lock
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Lock Indicator
No External Components Required for PLL
28-Pin SSOP and Space Saving 5
脳
5 mm QFN
Packages Available
Industrial Temperature Qualified, T
A
= 鈥?0擄C
to 85擄C
Programmable Edge Trigger on Clock
Flow-Through Pinout for Easy PCB Layout
鈥?/div>
鈥?/div>
鈥?/div>
DESCRIPTION
The SN65LV1023A serializer and SN65LV1224B deserializer comprise a 10-bit serdes chipset designed to
transmit and receive serial data over LVDS differential backplanes at equivalent parallel word rates from 10 MHz
to 66 MHz. Including overhead, this translates into a serial data rate between 120-Mbps and 792-Mbps payload
encoded throughput.
Upon power up, the chipset link can be initialized via a synchronization mode with internally generated SYNC
patterns or the deserializer can be allowed to synchronize to random data. By using the synchronization mode,
the deserializer establishes lock within specified, shorter time parameters.
The device can be entered into a power-down state when no data transfer is required. Alternatively, a mode is
available to place the output pins in the high-impedance state without losing PLL lock.
The SN65LV1023A and SN65LV1224B are characterized for operation over ambient air temperature of 鈥?0擄C to
85擄C.
SYNC2
SYNC1
DV
CC
DV
CC
DV
CC
DV
CC
SYNC1
SYNC2
D
IN0
D
IN1
D
IN2
D
IN3
D
IN4
D
IN5
D
IN6
D
IN7
D
IN8
D
IN9
TCLK_R/F
TCLK
1
28
2
27
3
26
4
25
5
24
6
23
DB Package 22
7
SN65LV1023A
8
21
Serializer
9
20
10
19
11
18
12
17
13
16
14
15
DV
CC
DV
CC
AV
CC
AGND
PWRDN
AGND
D
O
+
D
O
鈭?/div>
AGND
DEN
AGND
AV
CC
DGND
DGND
D
IN1
D
IN
2
D
IN
3
D
IN4
D
IN5
D
IN6
D
IN7
D
IN8
32 31 30 29 28 27 26 25
1
24
2
3
4
5
6
7
8
23
AV
CC
AGND
PWRDN
AGND
D
O+
D
O鈭?/div>
AGND
DEN
AGND
22
21
20
19
18
D
IN0
RHB Package
SN65LV1023A
Serializer
(Top View)
17
9 10 11 12 13 14 15 16
DGND
DGND
DGND
TCLK_R/F
DGND
TCLK
D
IN9
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright 漏 2004鈥?006, Texas Instruments Incorporated
AV
CC

SN65LV1224B PDF文件相關(guān)型號(hào)

SN65LVDS125A,SN65LVDS18,SN65LVDS19

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