SL74LS245
Octal 3-State Noninverting
Bus Transceiver
These octal bus transceiver are designed for asynchronous two-
way communication between data buses. The control function
implementation minimized external timing requirements.
The device allows data transmission from the A bus to the B bus or
from the B bus to the A bus depending upon the logic level at the
directional control (DIR) input. The enable input(E) can be used to
disable the device so that the buses are effectively isolated.
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Bidirectional Bus Transceiver in a High-Density 20-Pin Package
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3-state Outputs Dirve Bus Lines Directly
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P-N-P Inputs D-C Loading on Bus Lines
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Hysteresis at Bus Inputs Improve Noise Margins
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Typical Propagation Delay Times; Port to Port ... 8 ns
ORDERING INFORMATION
SL74LS245N Plastic
SL74LS245D SOIC
T
A
= 0擄 to 70擄 C
for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Control Inputs
Output
Enable
L
PIN 20=V
CC
PIN 10 = GND
Direction
L
Operation
Data Transmitted
from Bus B to Bus
A
Data Transmitted
from Bus A to Bus
B
Buses Isolated
(High Impedance
State)
L
H
H
X
X = don鈥檛 care
SLS
System Logic
Semiconductor
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SL74LS245相關(guān)型號PDF文件下載
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英文版
Octal 3-State Noninverting Buffer/Line Driver/Line Receiver
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英文版
Octal 3-State Noninverting Buffer/Line Driver/Line Receiver
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英文版
Quad 2-Input NAND Gate
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英文版
Quad 2-Input NAND Gate
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英文版
Quad 2-Input NOR Gate
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英文版
Quad 2-Input NOR Gate
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英文版
Quad 2-Input NAND Gate with Open-Drain Outputs
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英文版
Quad 2-Input NAND Gate with Open-Drain Outputs
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英文版
Hex Inverter High-Performance Silicon-Gate CMOS
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英文版
Hex Inverter High-Performance Silicon-Gate CMOS
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英文版
Hex Inverter with Open-Drain Outputs
SLS
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英文版
Hex Inverter with Open-Drain Outputs
SLS [Syste...
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英文版
Quad 2-Input AND Gate
SLS
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英文版
Quad 2-Input AND Gate
SLS [Syste...
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英文版
Triple 3-Input NAND Gate
SLS
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英文版
Triple 3-Input NAND Gate
SLS [Syste...
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英文版
Triple 3-Input AND Gate
SLS
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英文版
Triple 3-Input AND Gate
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