SL74LS138
3-to-8-Line
Decoder/Demultiplexer
This schottky-clamped TTL MSI circuit is designed to be used in
high-performance memory-decording or data-routing applications
requiring very short propagation delay time. In high-performance
memory systems this decode can be used to minimize the effects of
system decoding. When employed with high-speed memories utilizing
a fast enable circuit the delay times of this decorder and the enable time
of the memory are usually less than the typical access times of the
memory. This means that the effective system delay introduced by the
schottky-clampled system decoder is negligible.
鈥?/div>
Designed Specifically for High Speed Memory Decoders and Data
Transmission Systems
鈥?/div>
Incorporate 3 Enabler Inputs to Simplify Cascading AND/OR Data
Reception
鈥?/div>
Schottky Clamped for High Performance
ORDERING INFORMATION
SL74LS138N Plastic
SL74LS138D SOIC
T
A
= 0擄 to 70擄 C
for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Inputs
CS1 CS2 CS3
X X H
X H X
L X X
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
A2 A1 A0
X X X
X X X
X X X
L L L
L L H
L H L
L H H
H L L
H L H
H H L
H H H
Outputs
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
H H H H H H H H
H H H H H H H H
H H H H H H H H
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
PIN 16 =V
CC
PIN 8 = GND
L H H H
H L H H
H H L H
H H H L
H = high level (steady state)
L = low level (steady state)
X = don鈥檛 care
SLS
System Logic
Semiconductor
1
2
3
