音影先锋亚洲天堂网|电影世界尽头的爱完整版播放|国产 熟女 91|高清无码免费观看欧美日韩|韩国一区二区三区黄色录像|美女亚洲加勒比在线|亚洲综合网 开心五月|7x成人在线入口|成人网站免费日韩毛片区|国产黄片?一级?二级?三级

SI552 Datasheet

  • SI552

  • Silicon Laboratories [DUAL FREQUENCY VCXO (10 MHZ TO 1.4 GH...

  • SILABS

掃碼查看芯片數(shù)據(jù)手冊(cè)

上傳產(chǎn)品規(guī)格書(shū)

PDF預(yù)覽

Si552
P
R E L I M I N A R Y
D
A TA
S
H E E T
D
U A L
F
R E Q U E N C Y
VCXO (10 M H
Z
Features
Available with any-rate output
frequencies from 10 to 945 MHz and
selected frequencies to 1.4 GHz
Two selectable output frequencies
Industry-standard 7x5 mm package
Available CMOS, LVPECL, LVDS &
CML outputs
TO
1.4 GH
Z
)
3x better frequency stability than
SAW-based oscillators
3rd generation DSPLL
with
superior jitter performance
Internal fixed crystal frequency
ensures high reliability and low
aging
Lead-free/RoHS-compliant
Si5602
Applications
SONET / SDH
xDSL
10 GbE LAN / WAN
Low jitter clock generation
Optical Modules
Test and Measurement
Ordering Information:
See page 7.
Description
The Si552 dual frequency VCXO utilizes Silicon Laboratories advanced
DSPLL
circuitry to provide a very low jitter clock for all output frequencies.
The Si552 is available with any-rate output frequency from 10 to 945 MHz
and selected frequencies to 1400 MHz. Unlike traditional VCXO鈥檚 where a
different crystal is required for each output frequency, the Si552 uses one
fixed crystal frequency to provide a wide range of output frequencies. This
IC based approach allows the crystal resonator to be optimized for superior
frequency stability and reliability. In addition, DSPLL clock synthesis
provides superior supply noise rejection, simplifying the task of generating
low jitter clocks in noisy environments often found in communication
systems. The Si552 IC based VCXO is factory configurable for a wide
variety of user specifications including frequency, supply voltage and output
format. Specific configurations are factory programmed into the Si552 at
time of shipment, thereby eliminating the long lead times associated with
custom oscillators.
Functional Block Diagram
V
DD
CLK- CLK+
Fixed
Frequency XO
Any-rate
10鈥?400 MHz
DSPLL鈩?/div>
Clock Synthesis
ADC
V
C
FS
GND
Preliminary Rev. 0.2 8/05
Copyright 漏 2005 by Silicon Laboratories
Si552
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

SI552相關(guān)型號(hào)PDF文件下載

掃碼下載APP,
一鍵連接廣大的電子世界。

在線人工客服

買家服務(wù):
賣家服務(wù):
技術(shù)客服:

0571-85317607

網(wǎng)站技術(shù)支持

13606545031

客服在線時(shí)間周一至周五
9:00-17:30

關(guān)注官方微信號(hào),
第一時(shí)間獲取資訊。

建議反饋

聯(lián)系人:

聯(lián)系方式:

按住滑塊,拖拽到最右邊
>>
感謝您向阿庫(kù)提出的寶貴意見(jiàn),您的參與是維庫(kù)提升服務(wù)的動(dòng)力!意見(jiàn)一經(jīng)采納,將有感恩紅包奉上哦!