EW
SFH6318T
SFH6319T
LOW CURRENT, HIGH GAIN
OPTOCOUPLER
Package Dimensions in Inches (mm)
.120鹵.002
(3.05鹵.05)
NC
1
8
V
CC
7
V
B
6
V
0
5
GND
N
FEATURES
鈥?Industry Standard SOIC-8 Surface Mountable
Package
鈥?High Current Transfer Ratio, 800%
鈥?Low Input Current, 0.5mA
鈥?High Output Current, 60mA
鈥?Isolation Test Voltage, 2500 VAC
RMS
鈥?TTL Compatible Output, V
OL
=0.1 V
鈥?Adjustable Bandwidth-Access to Base
鈥?Underwriters Lab File #E52744
鈥?Available in Tape and Reel (suffix T)
APPLICATIONS
鈥?Logic Ground Isolation-TTL/TTL, TTL/CMOS,
CMOS/CMOS, CMOS/TTL
鈥?EIA RS 232C Line Receiver
鈥?Low Input Current Line Receiver-Long Lines,
Party Lines
鈥?Telephone Ring Detector
鈥?117 VAC Line Voltage Status Indication-Low
Input Power Dissipation
鈥?Low Power Systems-Ground Isolation
.240
(6.10)
C
.154鹵.002
L
(.391鹵.05)
.016
(.41)
.192鹵.005
(4.88鹵.13)
Anode
2
Cathode
3
NC
4
40擄
Pin 1
.015鹵.002
(.38鹵.05)
7擄
.058鹵.005
(1.49鹵.13)
.125鹵.005
(3.18鹵.13)
Lead
Coplanarity
鹵.0015
(.04
max.
.004 (.10)
.008 (.20)
.008 (.20)
5擄 max.
R.010
(.25)
max.
.021
(.53)
.050
(1.27)
typ.
.020鹵.004
(.15鹵.10)
2 plcs.
TOLERANCE:
鹵
.005 (unless otherwise noted)
DESCRIPTION
Very high current ratio together with 2500 VAC isolation
are achieved by coupling an LED with an integrated high
gain photodetector in a SOIC-8 package. Separate pins
for the photodiode and output stage enable TTL compat-
ible saturation voltages with high speed operation. Pho-
todarlington operation is achieved by tying the VCC and
VO terminals together. Access to the base terminal
allows adjustment to the gain bandwidth.
The SFH6318T is ideal for TTL applications since the
300% minimum current transfer ratio with an LED current
of 1.6 mA enables operation with one unit load-in and
one unit load-out with a 2.2 K鈩?pull-up resistor.
The SFH6319T is best suited for low power logic applica-
tions involving CMOS and low power TTL. A 400% cur-
rent transfer ratio with only 0.5 mA of LED current is
guaranteed from 0擄C to 70擄C.
Caution:
Due to the small geometries of this device, it should be
handled with Electrostatic Discharge (ESD) precautions.
Proper grounding would prevent damage further and/or
degradation which may be induced by ESD.
Maximum Ratings (25擄)
Emitter
Reverse Input Voltage.............................................................. 3 V
Supply and Output Voltage, V
CC
(pin 8-5), V
O
(pin 6-5)
SFH6318T ..................................................................鈥?.5 to 7 V
SFH6319T ................................................................鈥?.5 to 18 V
Input Power Dissipation ..................................................... 35 mW
Derate Linearly above 50擄C
Free Air Temperature................................................ 0.7 mW/擄C
Average Input Current......................................................... 20 mA
Peak Input Current .............................................................. 40 mA
(50% Duty Cycle-1 ms pulse width)
Peak Transient Input Current
(tp鈮?
碌sec,
300 pps) ......................................................... 1.0 A
Detector (Si Photodiode + Photodarlington)
Output Current I
O
(pin 6)..................................................... 60 mA
Emitter-Base Reverse Voltage (pin 5-7)................................ 0.5 V
Output Power Dissipation................................................. 150 mW
Derate Linearly from 25擄C ........................................... 2 mW/擄C
Package
Storage Temperature ......................................... 鈥?5擄C to +125擄C
Operating Temperature........................................ 鈥?0擄C to +85擄C
Lead Soldering Temperature (t=10 sec.).............................260擄C
Junction Temperature ..........................................................100擄C
Ambient Temperature Range............................. 鈥?5擄C to +100擄C
IsolationTest Voltage between
Emitter and Detector............................................ 2500 VAC
RMS
(refer to climate DIN 40046, part 2, Nov. 74)
Pollution Degree (DIN VDE 0110) ................................................2
Creepage Distance .............................................................鈮? mm
Clearance............................................................................鈮? mm
Comparative Tracking Index
per DIN IEC 112/VDE 0303, part 1 .......................................175
Isolation Resistance
V
IO
=500 V, T
A
=25擄C R
ISOL
.............................................鈮?0
12
鈩?/div>
V
IO
=500 V, T
A
=100擄C R
ISOL
...........................................鈮?0
11
鈩?/div>
Semiconductor Goup
4鈥?8
10.95
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